syv.syr

针对串行存储器M25P80应用的verilog程序

 5-bit adder                       : 3
 6-bit adder                       : 1
 9-bit adder                       : 1
# Counters                         : 3
 10-bit up counter                 : 1
 15-bit up counter                 : 1
 24-bit up counter                 : 1
# Registers                        : 87
 1-bit register                    : 80
 19-bit register                   : 1
 5-bit register                    : 3
 6-bit register                    : 1
 8-bit register                    : 1
 9-bit register                    : 1
# Comparators                      : 7
 15-bit comparator less            : 1
 24-bit comparator lessequal       : 1
 5-bit comparator less             : 3
 6-bit comparator less             : 1
 9-bit comparator less             : 1
# Multiplexers                     : 1
 1-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <syv> ...
Loading device for application Rf_Device from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block syv, actual ratio is 23.
FlipFlop div_clock_t has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : syv.ngr
Top Level Output File Name         : syv
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 58

Macro Statistics :
# Registers                        : 26
#      1-bit register              : 16
#      19-bit register             : 1
#      24-bit register             : 3
#      5-bit register              : 3
#      6-bit register              : 1
#      8-bit register              : 1
#      9-bit register              : 1
# Multiplexers                     : 1
#      1-bit 8-to-1 multiplexer    : 1
# Adders/Subtractors               : 9
#      19-bit adder                : 1
#      24-bit adder                : 3
#      5-bit adder                 : 3
#      6-bit adder                 : 1
#      9-bit adder                 : 1
# Comparators                      : 7
#      15-bit comparator less      : 1
#      24-bit comparator lessequal : 1
#      5-bit comparator less       : 3
#      6-bit comparator less       : 1
#      9-bit comparator less       : 1

Cell Usage :
# BELS                             : 532
#      GND                         : 1
#      INV                         : 14
#      LUT1                        : 88
#      LUT1_L                      : 3
#      LUT2                        : 28
#      LUT2_L                      : 2
#      LUT3                        : 26
#      LUT3_D                      : 3
#      LUT3_L                      : 11
#      LUT4                        : 70
#      LUT4_D                      : 11
#      LUT4_L                      : 85
#      MUXCY                       : 96
#      MUXF5                       : 3
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 89
# FlipFlops/Latches                : 187
#      FDE                         : 100
#      FDR                         : 68
#      FDRE                        : 9
#      FDRS                        : 6
#      FDRSE                       : 1
#      FDS                         : 3
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 46
#      IBUF                        : 9
#      OBUF                        : 37
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     196  out of    768    25%  
 Number of Slice Flip Flops:           187  out of   1536    12%  
 Number of 4 input LUTs:               327  out of   1536    21%  
 Number of bonded IOBs:                 58  out of     96    60%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
div_clock_t:Q                      | BUFG                   | 149   |
global_clk                         | BUFGP                  | 38    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.658ns (Maximum Frequency: 79.001MHz)
   Minimum input arrival time before clock: 6.112ns
   Maximum output required time after clock: 7.085ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_clock_t:Q'
  Clock period: 12.658ns (frequency: 79.001MHz)
  Total number of paths / destination ports: 5509 / 171
-------------------------------------------------------------------------
Delay:               12.658ns (Levels of Logic = 6)
  Source:            st_wr_FFd11 (FF)
  Destination:       led_chip1 (FF)
  Source Clock:      div_clock_t:Q rising
  Destination Clock: div_clock_t:Q rising

  Data Path: st_wr_FFd11 to led_chip1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  st_wr_FFd11 (st_wr_FFd11)
     LUT4:I3->O            1   0.549   1.035  Ker3421 (CHOICE193)
     LUT4_L:I0->LO         1   0.549   0.100  Ker3439_SW0 (N868)
     LUT4:I3->O           12   0.549   2.160  Ker3439 (N341)
     LUT4_D:I0->O          9   0.549   1.908  Ker3019 (N30)
     LUT4_D:I1->O          1   0.549   1.035  Ker51 (N5)
     LUT3_L:I1->LO         1   0.549   0.000  _n00851 (_n0085)
     FDS:D                     0.709          led_chip1
    ----------------------------------------
    Total                     12.658ns (5.088ns logic, 7.570ns route)
                                       (40.2% logic, 59.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'global_clk'
  Clock period: 9.928ns (frequency: 100.725MHz)
  Total number of paths / destination ports: 701 / 76
-------------------------------------------------------------------------
Delay:               9.928ns (Levels of Logic = 1)
  Source:            sys_reset (FF)
  Destination:       counter_6M_8 (FF)
  Source Clock:      global_clk rising
  Destination Clock: global_clk rising

  Data Path: sys_reset to counter_6M_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             80   1.085   5.580  sys_reset (sys_reset)
     LUT2:I0->O           10   0.549   1.980  _n00731 (_n0073)
     FDR:R                     0.734          counter_6M_0
    ----------------------------------------
    Total                      9.928ns (2.368ns logic, 7.560ns route)
                                       (23.9% logic, 76.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'div_clock_t:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              6.112ns (Levels of Logic = 4)
  Source:            datam25_fpga (PAD)
  Destination:       da_tp3_0 (FF)
  Destination Clock: div_clock_t:Q rising

  Data Path: datam25_fpga to da_tp3_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  datam25_fpga_IBUF (datam25_fpga_IBUF)
     LUT4:I3->O            8   0.549   1.845  Ker381 (N38)
     LUT4_L:I0->LO         1   0.549   0.100  _n009328 (CHOICE282)
     LUT4_L:I2->LO         1   0.549   0.000  _n009331 (_n0093)
     FDE:D                     0.709          da_tp3_0
    ----------------------------------------
    Total                      6.112ns (3.132ns logic, 2.980ns route)
                                       (51.2% logic, 48.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_clock_t:Q'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.085ns (Levels of Logic = 1)
  Source:            memaddr_18 (FF)
  Destination:       memaddr<18> (PAD)
  Source Clock:      div_clock_t:Q rising

  Data Path: memaddr_18 to memaddr<18>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   1.085   1.332  memaddr_18 (memaddr_18)
     OBUF:I->O                 4.668          memaddr_18_OBUF (memaddr<18>)
    ----------------------------------------
    Total                      7.085ns (5.753ns logic, 1.332ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'global_clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            div_clock (FF)
  Destination:       div_clock (PAD)
  Source Clock:      global_clk rising

  Data Path: div_clock to div_clock
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   1.085   1.206  div_clock (div_clock_OBUF)
     OBUF:I->O                 4.668          div_clock_OBUF (div_clock)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 16.61 / 17.08 s | Elapsed : 17.00 / 17.00 s
 
--> 

Total memory usage is 90992 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    3 (   0 filtered)