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来自「针对串行存储器M25P80应用的verilog程序」· LOG 代码 · 共 1,457 行 · 第 1/5 页
LOG
1,457 行
Process "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 127 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 127 expecting 'end', found '2'ERROR:HDLCompilers:26 - "syv.v" line 133 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 133 expecting 'end', found '3'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 135 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 133 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 133 expecting 'end', found '3'ERROR:HDLCompilers:26 - "syv.v" line 138 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 138 expecting 'end', found '4'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 140 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 138 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 138 expecting 'end', found '4'ERROR:HDLCompilers:26 - "syv.v" line 143 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 143 expecting 'end', found '5'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 145 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 148 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 148 expecting 'end', found '6'ERROR:HDLCompilers:26 - "syv.v" line 153 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 153 expecting 'end', found '7'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 155 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 256 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 256 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 257 unexpected token: '{'ERROR:HDLCompilers:28 - "syv.v" line 258 'w_addr24' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 260 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 266 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 267 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 268 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 269 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 272 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 274 expecting 'end', found '}'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 276 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 14 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 257 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 258 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 261 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 267 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 267 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 268 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 269 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 269 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 270 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 273 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 275 expecting 'end', found '}'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 277 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 13 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 257 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 258 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 261 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 267 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 267 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 268 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 269 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 269 expecting ';', found ')'ERROR:HDLCompilers:26 - "syv.v" line 270 unexpected token: '{'ERROR:HDLCompilers:26 - "syv.v" line 273 expecting 'end', found '}'ERROR:HDLCompilers:26 - "syv.v" line 275 expecting 'end', found '}'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 277 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 13 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.⌨️ 快捷键说明
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