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Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 83 expecting 'endmodule', found '@'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 13 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:28 - "syv.v" line 74 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 80 'sys_reset' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 84 expecting 'end', found 'always'ERROR:HDLCompilers:208 - "syv.v" line 29 Port reference 'led1' was not declared as input, inout or outputERROR:HDLCompilers:208 - "syv.v" line 24 Port reference 'div_clock' was not declared as input, inout or outputModule <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 84 expecting 'endmodule', found '@'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 6 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:28 - "syv.v" line 102 'counter_50M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 102 'counter_50M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 111 'wr' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 113 'st_wr' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 119 'st_wr' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 123 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 123 expecting 'end', found '1'ERROR:HDLCompilers:28 - "syv.v" line 125 'st_wr' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 128 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 128 expecting 'end', found '2'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 131 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 11 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:28 - "syv.v" line 89 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 94 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 96 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 111 'wr' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 113 'st_wr' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 119 'st_wr' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 123 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 123 expecting 'end', found '1'ERROR:HDLCompilers:28 - "syv.v" line 125 'st_wr' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 128 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 128 expecting 'end', found '2'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 131 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 12 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 122 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 122 expecting 'end', found '1'ERROR:HDLCompilers:26 - "syv.v" line 127 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 127 expecting 'end', found '2'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 130 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 127 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 127 expecting 'end', found '2'ERROR:HDLCompilers:26 - "syv.v" line 133 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 133 expecting 'end', found '3'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 135 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 127 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 127 expecting 'end', found '2'ERROR:HDLCompilers:26 - "syv.v" line 133 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 133 expecting 'end', found '3'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 135 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 127 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 127 expecting 'end', found '2'ERROR:HDLCompilers:26 - "syv.v" line 133 unexpected token: 'st_wr'ERROR:HDLCompilers:26 - "syv.v" line 133 expecting 'end', found '3'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 135 expecting 'endmodule', found 'if'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failed⌨️ 快捷键说明
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