ps2tolcd.tan.qmsg

VHDL语言实现的程序

{ "Info" "ITDB_TSU_RESULT" "div_256:inst1\|clk reset mclk 8.240 ns register " "Info: tsu for register \"div_256:inst1\|clk\" (data pin = \"reset\", clock pin = \"mclk\") is 8.240 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.423 ns + Longest pin register " "Info: + Longest pin to register delay is 11.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns reset 1 PIN PIN_AA3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA3; Fanout = 43; PIN Node = 'reset'" {  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "" { reset } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/code/EP2C35/S9_PS2_LCD/PROJ/ps2tolcd.bdf" { { 280 -176 -8 296 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.617 ns) + CELL(0.872 ns) 11.423 ns div_256:inst1\|clk 2 REG LCFF_X31_Y35_N1 1 " "Info: 2: + IC(9.617 ns) + CELL(0.872 ns) = 11.423 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "10.489 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/code/EP2C35/S9_PS2_LCD/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns 15.81 % " "Info: Total cell delay = 1.806 ns ( 15.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.617 ns 84.19 % " "Info: Total interconnect delay = 9.617 ns ( 84.19 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "11.423 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.423 ns" { reset reset~combout div_256:inst1|clk } { 0.000ns 0.000ns 9.617ns } { 0.000ns 0.934ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../SRC/div_256.v" "" { Text "E:/code/EP2C35/S9_PS2_LCD/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.143 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 3.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/code/EP2C35/S9_PS2_LCD/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns mclk~clkctrl 2 COMB CLKCTRL_G14 8 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G14; Fanout = 8; COMB Node = 'mclk~clkctrl'" {  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "0.132 ns" { mclk mclk~clkctrl } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/code/EP2C35/S9_PS2_LCD/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.679 ns) 3.143 ns div_256:inst1\|clk 3 REG LCFF_X31_Y35_N1 1 " "Info: 3: + IC(1.232 ns) + CELL(0.679 ns) = 3.143 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "1.911 ns" { mclk~clkctrl div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/code/EP2C35/S9_PS2_LCD/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.60 % " "Info: Total cell delay = 1.779 ns ( 56.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.364 ns 43.40 % " "Info: Total interconnect delay = 1.364 ns ( 43.40 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "3.143 ns" { mclk mclk~clkctrl div_256:inst1|clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.143 ns" { mclk mclk~combout mclk~clkctrl div_256:inst1|clk } { 0.000ns 0.000ns 0.132ns 1.232ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP2C35/S9_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP2C35/S9_PS2_LCD/PROJ/" "" "11.423 ns" { reset div_256:inst1|clk } "NODE_NAME"