lcd_v.map.qmsg

FPGA实现的LCD接口

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 11 23:28:32 2007 " "Info: Processing started: Sun Feb 11 23:28:32 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_v -c lcd_v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_v -c lcd_v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DIV16.v" { { "Info" "ISGN_ENTITY_NAME" "1 div16 " "Info: Found entity 1: div16" {  } { { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div200.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div200.v" { { "Info" "ISGN_ENTITY_NAME" "1 div200 " "Info: Found entity 1: div200" {  } { { "div200.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/div200.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_v.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_v.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_v " "Info: Found entity 1: lcd_v" {  } { { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_v " "Info: Elaborating entity \"lcd_v\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst1 " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst1\"" {  } { { "lcd_v.bdf" "inst1" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 104 288 400 232 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 lcd.v(78) " "Warning: Verilog HDL assignment warning at lcd.v(78): truncated value with size 32 to match size of target (16)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(82) " "Warning: Verilog HDL assignment warning at lcd.v(82): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(87) " "Warning: Verilog HDL assignment warning at lcd.v(87): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(94) " "Warning: Verilog HDL assignment warning at lcd.v(94): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(100) " "Warning: Verilog HDL assignment warning at lcd.v(100): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(110) " "Warning: Verilog HDL assignment warning at lcd.v(110): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(120) " "Warning: Verilog HDL assignment warning at lcd.v(120): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 120 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(125) " "Warning: Verilog HDL assignment warning at lcd.v(125): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(127) " "Warning: Verilog HDL assignment warning at lcd.v(127): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 127 0 0 } }  } 0}