colorbar.vo

用FPGA实现的VGA接口程序

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "08/23/2008 20:22:29"

// 
// Device: Altera EP2C35F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ColorBar (
	rst,
	clk,
	VGA_HS,
	VGA_VS,
	VGA_BLANK,
	VGA_CLK,
	RGB,
	VGA_RGB);
input 	rst;
input 	clk;
output 	VGA_HS;
output 	VGA_VS;
output 	VGA_BLANK;
output 	VGA_CLK;
output 	[12:0] RGB;
output 	[2:0] VGA_RGB;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ColorBar_v.sdo");
// synopsys translate_on

wire \inst4|altpll_component|_clk1 ;
wire \inst4|altpll_component|_clk2 ;
wire \inst|LessThan~2058 ;
wire \inst|LessThan~2062 ;
wire \inst|LessThan~2063 ;
wire \inst|LessThan~2064 ;
wire \inst|hcnt[3] ;
wire \inst|always3~74 ;
wire \inst|always4~145 ;
wire \inst|always4~146 ;
wire \inst|LessThan~2069 ;
wire \inst|hcnt[3]~256 ;
wire \inst|hcnt[5]~272 ;
wire \clk~combout ;
wire \inst4|altpll_component|_clk0 ;
wire \inst4|altpll_component|_clk0~clkctrl ;
wire \inst|hcnt[0]~251 ;
wire \inst|hcnt[1]~252 ;
wire \rst~combout ;
wire \inst|hcnt[7]~264 ;
wire \inst|hcnt[7] ;
wire \inst|hcnt[5]~249 ;
wire \inst|hcnt[9]~269 ;
wire \inst|hcnt[10]~270 ;
wire \inst|hcnt[10] ;
wire \inst|LessThan~2071 ;
wire \inst|hcnt[1] ;
wire \inst|hcnt[1]~253 ;
wire \inst|hcnt[2]~254 ;
wire \inst|hcnt[2] ;
wire \inst|hcnt[2]~255 ;
wire \inst|hcnt[3]~257 ;
wire \inst|hcnt[4]~258 ;
wire \inst|hcnt[4] ;
wire \inst|hcnt[4]~259 ;
wire \inst|hcnt[5]~261 ;
wire \inst|hcnt[6]~262 ;
wire \inst|hcnt[6] ;
wire \inst|hcnt[6]~263 ;
wire \inst|hcnt[7]~265 ;
wire \inst|hcnt[8]~266 ;
wire \inst|hcnt[8] ;
wire \inst|hcnt[8]~267 ;
wire \inst|hcnt[9]~268 ;
wire \inst|hcnt[9] ;
wire \inst|always4~144 ;
wire \inst|hcnt[5]~260 ;
wire \inst|hcnt[5] ;
wire \inst|hcnt[0]~250 ;
wire \inst|hcnt[0] ;
wire \inst|always1~295 ;
wire \inst|always1~296 ;
wire \inst|always1~297 ;
wire \inst|hsyncint ;
wire \inst|hsyncint~clkctrl ;
wire \inst|vcnt[0]~431 ;
wire \inst|vcnt[1]~432 ;
wire \inst|vcnt[7]~445 ;
wire \inst|vcnt[8]~446 ;
wire \inst|vcnt[8] ;
wire \inst|vcnt[8]~447 ;
wire \inst|vcnt[9]~448 ;
wire \inst|vcnt[9] ;
wire \inst|vcnt[9]~449 ;
wire \inst|vcnt[10]~450 ;
wire \inst|vcnt[10] ;
wire \inst|LessThan~2061 ;
wire \inst|LessThan~2070 ;
wire \inst|vcnt[1] ;
wire \inst|vcnt[1]~433 ;
wire \inst|vcnt[2]~435 ;
wire \inst|vcnt[3]~437 ;
wire \inst|vcnt[4]~438 ;
wire \inst|vcnt[4] ;
wire \inst|vcnt[4]~439 ;
wire \inst|vcnt[5]~441 ;
wire \inst|vcnt[6]~442 ;
wire \inst|vcnt[6] ;
wire \inst|vcnt[6]~443 ;
wire \inst|vcnt[7]~444 ;
wire \inst|vcnt[7] ;
wire \inst|always3~73 ;
wire \inst|vcnt[2]~434 ;
wire \inst|vcnt[2] ;
wire \inst|vcnt[0]~430 ;
wire \inst|vcnt[0] ;
wire \inst|LessThan~2066 ;
wire \inst|vcnt[1]~429 ;
wire \inst|always3~75 ;
wire \inst|vsync ;
wire \inst|vcnt[5]~440 ;
wire \inst|vcnt[5] ;
wire \inst|always4~147 ;
wire \inst|always4~143 ;
wire \inst|always4~148 ;
wire \inst|always4~149 ;
wire \inst|enable ;
wire \inst|vcnt[1]~428 ;
wire \inst|vcnt[3]~436 ;
wire \inst|vcnt[3] ;
wire \inst|pixel[0]~1333 ;
wire \inst|LessThan~2065 ;
wire \inst|pixel~1334 ;
wire \inst|pixel[2]~1335 ;
wire \inst|LessThan~2059 ;
wire \inst|LessThan~2060 ;
wire \inst|pixel[2]~1332 ;
wire \inst|pixel[1]~1336 ;
wire \inst|pixel[2]~1337 ;
wire \inst|LessThan~2068 ;
wire \inst|pixel[1]~1338 ;
wire \inst|pixel[1]~1339 ;
wire \inst|LessThan~2067 ;
wire \inst|pixel[0]~1341 ;
wire \inst|pixel[0]~1342 ;
wire \inst|pixel[0]~1343 ;
wire \inst|pixel[0]~1344 ;
wire \inst|pixel[0]~1345 ;
wire \inst|pixel[0]~1346 ;
wire \inst|pixel[0]~1340 ;
wire \inst|pixel[0]~1347 ;

wire [2:0] \inst4|altpll_component|pll_CLK_bus ;

assign \inst4|altpll_component|_clk0  = \inst4|altpll_component|pll_CLK_bus [0];
assign \inst4|altpll_component|_clk1  = \inst4|altpll_component|pll_CLK_bus [1];
assign \inst4|altpll_component|_clk2  = \inst4|altpll_component|pll_CLK_bus [2];

// atom is at LCCOMB_X22_Y11_N20
cycloneii_lcell_comb \inst|LessThan~2058_I (
// Equation(s):
// \inst|LessThan~2058  = !\inst|vcnt[8]  & (!\inst|vcnt[6]  # !\inst|vcnt[5]  # !\inst|vcnt[7] )

	.dataa(\inst|vcnt[8] ),
	.datab(\inst|vcnt[7] ),
	.datac(\inst|vcnt[5] ),
	.datad(\inst|vcnt[6] ),
	.cin(gnd),
	.combout(\inst|LessThan~2058 ),
	.cout());
// synopsys translate_off
defparam \inst|LessThan~2058_I .sum_lutc_input = "datac";
defparam \inst|LessThan~2058_I .lut_mask = 16'h1555;
// synopsys translate_on

// atom is at LCCOMB_X23_Y11_N20
cycloneii_lcell_comb \inst|LessThan~2062_I (
// Equation(s):
// \inst|LessThan~2062  = !\inst|vcnt[6]  & !\inst|vcnt[8]  & !\inst|vcnt[5] 

	.dataa(\inst|vcnt[6] ),
	.datab(\inst|vcnt[8] ),
	.datac(vcc),
	.datad(\inst|vcnt[5] ),
	.cin(gnd),
	.combout(\inst|LessThan~2062 ),
	.cout());
// synopsys translate_off
defparam \inst|LessThan~2062_I .sum_lutc_input = "datac";
defparam \inst|LessThan~2062_I .lut_mask = 16'h0011;
// synopsys translate_on

// atom is at LCCOMB_X22_Y10_N10
cycloneii_lcell_comb \inst|LessThan~2063_I (
// Equation(s):
// \inst|LessThan~2063  = !\inst|vcnt[3]  & \inst|LessThan~2062  & (!\inst|vcnt[1]  # !\inst|vcnt[2] )

	.dataa(\inst|vcnt[3] ),
	.datab(\inst|vcnt[2] ),
	.datac(\inst|vcnt[1] ),
	.datad(\inst|LessThan~2062 ),
	.cin(gnd),
	.combout(\inst|LessThan~2063 ),
	.cout());
// synopsys translate_off
defparam \inst|LessThan~2063_I .sum_lutc_input = "datac";
defparam \inst|LessThan~2063_I .lut_mask = 16'h1500;
// synopsys translate_on

// atom is at LCCOMB_X22_Y10_N30
cycloneii_lcell_comb \inst|LessThan~2064_I (
// Equation(s):
// \inst|LessThan~2064  = \inst|LessThan~2061  # \inst|LessThan~2063  # \inst|LessThan~2062  & !\inst|vcnt[4] 

	.dataa(\inst|LessThan~2062 ),
	.datab(\inst|LessThan~2061 ),
	.datac(\inst|vcnt[4] ),
	.datad(\inst|LessThan~2063 ),
	.cin(gnd),
	.combout(\inst|LessThan~2064 ),
	.cout());
// synopsys translate_off
defparam \inst|LessThan~2064_I .sum_lutc_input = "datac";
defparam \inst|LessThan~2064_I .lut_mask = 16'hFFCE;
// synopsys translate_on

// atom is at LCFF_X24_Y8_N13
cycloneii_lcell_ff \inst|hcnt[3]~I (
	.clk(\inst4|altpll_component|_clk0~clkctrl ),
	.datain(\inst|hcnt[3]~256 ),
	.sdata(),
	.aclr(!\rst~combout ),
	.sclr(\inst|LessThan~2071 ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\inst|hcnt[3] ));

// atom is at LCCOMB_X22_Y10_N20
cycloneii_lcell_comb \inst|always3~74_I (
// Equation(s):
// \inst|always3~74  = \inst|vcnt[5]  # !\inst|vcnt[6]  # !\inst|vcnt[4] 

	.dataa(vcc),
	.datab(\inst|vcnt[4] ),
	.datac(\inst|vcnt[5] ),
	.datad(\inst|vcnt[6] ),
	.cin(gnd),
	.combout(\inst|always3~74 ),
	.cout());
// synopsys translate_off
defparam \inst|always3~74_I .sum_lutc_input = "datac";
defparam \inst|always3~74_I .lut_mask = 16'hF3FF;
// synopsys translate_on

// atom is at LCCOMB_X23_Y8_N0
cycloneii_lcell_comb \inst|always4~145_I (
// Equation(s):
// \inst|always4~145  = \inst|hcnt[3]  # \inst|hcnt[4]  # \inst|hcnt[1]  & \inst|hcnt[2] 

	.dataa(\inst|hcnt[1] ),
	.datab(\inst|hcnt[3] ),
	.datac(\inst|hcnt[2] ),
	.datad(\inst|hcnt[4] ),
	.cin(gnd),
	.combout(\inst|always4~145 ),
	.cout());
// synopsys translate_off
defparam \inst|always4~145_I .sum_lutc_input = "datac";
defparam \inst|always4~145_I .lut_mask = 16'hFFEC;
// synopsys translate_on

// atom is at LCCOMB_X23_Y10_N28
cycloneii_lcell_comb \inst|always4~146_I (
// Equation(s):
// \inst|always4~146  = \inst|always4~144  & (\inst|hcnt[5]  & \inst|always4~145  # !\inst|hcnt[5]~249 )

	.dataa(\inst|always4~144 ),
	.datab(\inst|hcnt[5] ),
	.datac(\inst|always4~145 ),
	.datad(\inst|hcnt[5]~249 ),
	.cin(gnd),
	.combout(\inst|always4~146 ),
	.cout());
// synopsys translate_off
defparam \inst|always4~146_I .sum_lutc_input = "datac";
defparam \inst|always4~146_I .lut_mask = 16'h80AA;
// synopsys translate_on

// atom is at LCCOMB_X22_Y10_N24
cycloneii_lcell_comb \inst|LessThan~2069_I (
// Equation(s):
// \inst|LessThan~2069  = !\inst|vcnt[3]  & !\inst|vcnt[2]  # !\inst|always4~143  # !\inst|vcnt[5] 

	.dataa(\inst|vcnt[5] ),
	.datab(\inst|vcnt[3] ),
	.datac(\inst|vcnt[2] ),
	.datad(\inst|always4~143 ),
	.cin(gnd),
	.combout(\inst|LessThan~2069 ),
	.cout());
// synopsys translate_off
defparam \inst|LessThan~2069_I .sum_lutc_input = "datac";
defparam \inst|LessThan~2069_I .lut_mask = 16'h57FF;
// synopsys translate_on

// atom is at LCCOMB_X24_Y8_N12
cycloneii_lcell_comb \inst|hcnt[3]~256_I (
// Equation(s):
// \inst|hcnt[3]~256  = \inst|hcnt[3]  & !\inst|hcnt[2]~255  # !\inst|hcnt[3]  & (\inst|hcnt[2]~255  # GND)
// \inst|hcnt[3]~257  = CARRY(!\inst|hcnt[2]~255  # !\inst|hcnt[3] )

	.dataa(\inst|hcnt[3] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\inst|hcnt[2]~255 ),
	.combout(\inst|hcnt[3]~256 ),
	.cout(\inst|hcnt[3]~257 ));
// synopsys translate_off
defparam \inst|hcnt[3]~256_I .sum_lutc_input = "cin";
defparam \inst|hcnt[3]~256_I .lut_mask = 16'h5A5F;
// synopsys translate_on

// atom is at LCCOMB_X25_Y8_N4
cycloneii_lcell_comb \inst|hcnt[5]~272_I (
// Equation(s):
// \inst|hcnt[5]~272  = !\inst|hcnt[8]  & !\inst|hcnt[5] 

	.dataa(vcc),
	.datab(\inst|hcnt[8] ),
	.datac(vcc),
	.datad(\inst|hcnt[5] ),
	.cin(gnd),
	.combout(\inst|hcnt[5]~272 ),
	.cout());
// synopsys translate_off
defparam \inst|hcnt[5]~272_I .sum_lutc_input = "datac";
defparam \inst|hcnt[5]~272_I .lut_mask = 16'h0033;
// synopsys translate_on

// atom is at PIN_W12
cycloneii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PLL_4
cycloneii_pll \inst4|altpll_component|pll (
	.ena(vcc),
	.clkswitch(gnd),
	.areset(gnd),
	.pfdena(vcc),
	.testclearlock(),
	.sbdin(),
	.inclk({gnd,\clk~combout }),
	.locked(),
	.testupout(),
	.testdownout(),
	.sbdout(),
	.clk(\inst4|altpll_component|pll_CLK_bus ));
// synopsys translate_off
defparam \inst4|altpll_component|pll .operation_mode = "normal";
defparam \inst4|altpll_component|pll .valid_lock_multiplier = 1;
defparam \inst4|altpll_component|pll .invalid_lock_multiplier = 5;
defparam \inst4|altpll_component|pll .compensate_clock = "clk0";
defparam \inst4|altpll_component|pll .inclk0_input_frequency = 20000;
defparam \inst4|altpll_component|pll .inclk1_input_frequency = 20000;
defparam \inst4|altpll_component|pll .pfd_min = 3333;
defparam \inst4|altpll_component|pll .pfd_max = 90909;
defparam \inst4|altpll_component|pll .vco_min = 1000;
defparam \inst4|altpll_component|pll .vco_max = 2000;
defparam \inst4|altpll_component|pll .vco_center = 1333;
defparam \inst4|altpll_component|pll .pll_compensation_delay = 5792;
defparam \inst4|altpll_component|pll .gate_lock_signal = "no";
defparam \inst4|altpll_component|pll .gate_lock_counter = 0;
defparam \inst4|altpll_component|pll .self_reset_on_gated_loss_lock = "off";
defparam \inst4|altpll_component|pll .m = 16;
defparam \inst4|altpll_component|pll .n = 1;
defparam \inst4|altpll_component|pll .charge_pump_current = 80;
defparam \inst4|altpll_component|pll .loop_filter_c = 3;
defparam \inst4|altpll_component|pll .loop_filter_r = " 2.500000";