freq_dev.map.rpt

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析

+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                       ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path          ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; freq_dev.vhd                     ; yes             ; User VHDL File  ; E:/tool_stud/freq_dev/freq_dev.vhd    ;
; count.vhd                        ; yes             ; Other           ; E:/tool_stud/freq_dev/count.vhd       ;
; detect_high.vhd                  ; yes             ; Other           ; E:/tool_stud/freq_dev/detect_high.vhd ;
; freq_cnt.vhd                     ; yes             ; Other           ; E:/tool_stud/freq_dev/freq_cnt.vhd    ;
+----------------------------------+-----------------+-----------------+---------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 231   ;
; Total combinational functions               ; 231   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 37    ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 190   ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 127   ;
;     -- arithmetic mode                      ; 104   ;
; Total registers                             ; 192   ;
; I/O pins                                    ; 84    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 192   ;
; Total fan-out                               ; 1163  ;
; Average fan-out                             ; 2.29  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                      ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
; |freq_dev                  ; 231 (83)          ; 192 (55)     ; 0           ; 0    ; 0            ; 0       ; 0         ; 84   ; 0            ; |freq_dev                ;
;    |count:U1|              ; 37 (37)           ; 28 (28)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |freq_dev|count:U1       ;
;    |detect_high:U2|        ; 56 (56)           ; 54 (54)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |freq_dev|detect_high:U2 ;
;    |freq_cnt:U3|           ; 55 (55)           ; 55 (55)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |freq_dev|freq_cnt:U3    ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 192   ;
; Number of registers using Synchronous Clear  ; 81    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 81    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|freq_cnt:U3|freq[0]         ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|freq_cnt:U3|count_int[25]   ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|cycle[0]~reg0               ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|count_int[12]               ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|detect_high:U2|high_time[0] ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|count:U1|count_int[13]      ;
; 3:1                ; 27 bits   ; 54 LEs        ; 27 LEs               ; 27 LEs                 ; Yes        ; |freq_dev|detect_high:U2|count_int[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 09 22:19:04 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq_dev -c freq_dev
Info: Found 2 design units, including 1 entities, in source file freq_dev.vhd
    Info: Found design unit 1: freq_dev-freq_top
    Info: Found entity 1: freq_dev
Info: Elaborating entity "freq_dev" for the top level hierarchy
Warning: Using design file count.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: count-counter
    Info: Found entity 1: count
Info: Elaborating entity "count" for hierarchy "count:U1"
Warning: Using design file detect_high.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: detect_high-plus_cnt
    Info: Found entity 1: detect_high
Info: Elaborating entity "detect_high" for hierarchy "detect_high:U2"
Warning: Using design file freq_cnt.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: freq_cnt-freq_detect
    Info: Found entity 1: freq_cnt
Info: Elaborating entity "freq_cnt" for hierarchy "freq_cnt:U3"
Info: Duplicate registers merged to single register
    Info: Duplicate register "freq_cnt:U3|signel_buf" merged to single register "signel_buf"
    Info: Duplicate register "detect_high:U2|enable_buf" merged to single register "signel_buf"
Info: Implemented 317 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 81 output pins
    Info: Implemented 233 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Mon Jun 09 22:19:12 2008
    Info: Elapsed time: 00:00:09