freq_dev.vhd

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY freq_dev IS
	PORT(
			clk : IN std_logic;
			reset : IN std_logic;
			signel : IN std_logic;
			freq : OUT std_logic_vector(26 downto 0);
			cycle : OUT std_logic_vector(26 downto 0);
			Hwith : OUT std_logic_vector(26 downto 0)
		);
END freq_dev;

ARCHITECTURE freq_top OF freq_dev IS

component count
		port(
				clk : IN std_logic;
				reset : IN std_logic;
				plus_1s : OUT std_logic
			);
end component;

component detect_high
		PORT(
				clk : IN std_logic;
				reset : IN std_logic;
				enable : IN std_logic;
				high_time : OUT std_logic_vector(26 downto 0)
			);
end component;

component freq_cnt
		PORT(
				clk : IN std_logic;
				reset : IN std_logic;
				signel : IN std_logic;
				lock : IN std_logic;
				freq : OUT std_logic_vector(26 downto 0)
			);
end component;

signal Plus1S:std_logic;
SIGNAL count_int:std_logic_vector(26 downto 0); --std_logic_vector(0 to 26);
signal signel_buf:std_logic;
--signal Hwith_buf : std_logic_vector(26 downto 0);

BEGIN
	U1:count PORT map(
						clk,
						reset,
						Plus1S
					);
	U2:detect_high PORT map(
								clk,
								reset,
								signel,
								Hwith
							);
	U3:freq_cnt PORT map(
							clk,
							reset,
							signel,
							Plus1S,
							freq
						);
	
	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		signel_buf <= signel ;
	END PROCESS;
	
	

	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			count_int <= (OTHERS => '0');
		ELSIF signel_buf = '0' AND signel = '1' THEN
			count_int <= (OTHERS => '0');
			ELSE
				count_int <= count_int + 1;
		END IF;
	END PROCESS;
	
	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			cycle <= (OTHERS => '0');
		ELSIF signel_buf = '0' AND signel = '1' THEN
			     cycle <= count_int + 1;
		END IF;
	END PROCESS;
		
	
	
END freq_top;