freq_dev.map.qmsg

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 09 22:19:04 2008 " "Info: Processing started: Mon Jun 09 22:19:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freq_dev -c freq_dev " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq_dev -c freq_dev" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_dev.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_dev.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_dev-freq_top " "Info: Found design unit 1: freq_dev-freq_top" {  } { { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_dev " "Info: Found entity 1: freq_dev" {  } { { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freq_dev " "Info: Elaborating entity \"freq_dev\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "count.vhd 2 1 " "Warning: Using design file count.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-counter " "Info: Found design unit 1: count-counter" {  } { { "count.vhd" "" { Text "E:/tool_stud/freq_dev/count.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "count.vhd" "" { Text "E:/tool_stud/freq_dev/count.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count count:U1 " "Info: Elaborating entity \"count\" for hierarchy \"count:U1\"" {  } { { "freq_dev.vhd" "U1" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 51 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "detect_high.vhd 2 1 " "Warning: Using design file detect_high.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 detect_high-plus_cnt " "Info: Found design unit 1: detect_high-plus_cnt" {  } { { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 detect_high " "Info: Found entity 1: detect_high" {  } { { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detect_high detect_high:U2 " "Info: Elaborating entity \"detect_high\" for hierarchy \"detect_high:U2\"" {  } { { "freq_dev.vhd" "U2" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "freq_cnt.vhd 2 1 " "Warning: Using design file freq_cnt.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_cnt-freq_detect " "Info: Found design unit 1: freq_cnt-freq_detect" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_cnt " "Info: Found entity 1: freq_cnt" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_cnt freq_cnt:U3 " "Info: Elaborating entity \"freq_cnt\" for hierarchy \"freq_cnt:U3\"" {  } { { "freq_dev.vhd" "U3" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "freq_cnt:U3\|signel_buf signel_buf " "Info: Duplicate register \"freq_cnt:U3\|signel_buf\" merged to single register \"signel_buf\"" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "detect_high:U2\|enable_buf signel_buf " "Info: Duplicate register \"detect_high:U2\|enable_buf\" merged to single register \"signel_buf\"" {  } { { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "317 " "Info: Implemented 317 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "81 " "Info: Implemented 81 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "233 " "Info: Implemented 233 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 09 22:19:12 2008 " "Info: Processing ended: Mon Jun 09 22:19:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}