freq_dev.tan.qmsg

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析

{ "Info" "ITDB_FULL_TCO_RESULT" "clk freq\[1\] freq_cnt:U3\|freq\[1\] 9.862 ns register " "Info: tco from clock \"clk\" to destination pin \"freq\[1\]\" through register \"freq_cnt:U3\|freq\[1\]\" is 9.862 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.849 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 192 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 192; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.666 ns) 2.849 ns freq_cnt:U3\|freq\[1\] 3 REG LCFF_X10_Y13_N7 1 " "Info: 3: + IC(0.904 ns) + CELL(0.666 ns) = 2.849 ns; Loc. = LCFF_X10_Y13_N7; Fanout = 1; REG Node = 'freq_cnt:U3\|freq\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clk~clkctrl freq_cnt:U3|freq[1] } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.39 % ) " "Info: Total cell delay = 1.806 ns ( 63.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.043 ns ( 36.61 % ) " "Info: Total interconnect delay = 1.043 ns ( 36.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl freq_cnt:U3|freq[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.849 ns" { clk clk~combout clk~clkctrl freq_cnt:U3|freq[1] } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.709 ns + Longest register pin " "Info: + Longest register to pin delay is 6.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freq_cnt:U3\|freq\[1\] 1 REG LCFF_X10_Y13_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N7; Fanout = 1; REG Node = 'freq_cnt:U3\|freq\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { freq_cnt:U3|freq[1] } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.443 ns) + CELL(3.266 ns) 6.709 ns freq\[1\] 2 PIN PIN_77 0 " "Info: 2: + IC(3.443 ns) + CELL(3.266 ns) = 6.709 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'freq\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.709 ns" { freq_cnt:U3|freq[1] freq[1] } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 48.68 % ) " "Info: Total cell delay = 3.266 ns ( 48.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.443 ns ( 51.32 % ) " "Info: Total interconnect delay = 3.443 ns ( 51.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.709 ns" { freq_cnt:U3|freq[1] freq[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.709 ns" { freq_cnt:U3|freq[1] freq[1] } { 0.000ns 3.443ns } { 0.000ns 3.266ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl freq_cnt:U3|freq[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.849 ns" { clk clk~combout clk~clkctrl freq_cnt:U3|freq[1] } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.709 ns" { freq_cnt:U3|freq[1] freq[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.709 ns" { freq_cnt:U3|freq[1] freq[1] } { 0.000ns 3.443ns } { 0.000ns 3.266ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "freq_cnt:U3\|freq\[25\] reset clk -0.344 ns register " "Info: th for register \"freq_cnt:U3\|freq\[25\]\" (data pin = \"reset\", clock pin = \"clk\") is -0.344 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.849 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 192 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 192; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.666 ns) 2.849 ns freq_cnt:U3\|freq\[25\] 3 REG LCFF_X9_Y13_N29 1 " "Info: 3: + IC(0.904 ns) + CELL(0.666 ns) = 2.849 ns; Loc. = LCFF_X9_Y13_N29; Fanout = 1; REG Node = 'freq_cnt:U3\|freq\[25\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.570 ns" { clk~clkctrl freq_cnt:U3|freq[25] } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.39 % ) " "Info: Total cell delay = 1.806 ns ( 63.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.043 ns ( 36.61 % ) " "Info: Total interconnect delay = 1.043 ns ( 36.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl freq_cnt:U3|freq[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.849 ns" { clk clk~combout clk~clkctrl freq_cnt:U3|freq[25] } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.499 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns reset 1 PIN PIN_129 114 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_129; Fanout = 114; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(0.202 ns) 3.391 ns freq_cnt:U3\|freq~1216 2 COMB LCCOMB_X9_Y13_N28 1 " "Info: 2: + IC(2.039 ns) + CELL(0.202 ns) = 3.391 ns; Loc. = LCCOMB_X9_Y13_N28; Fanout = 1; COMB Node = 'freq_cnt:U3\|freq~1216'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.241 ns" { reset freq_cnt:U3|freq~1216 } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.499 ns freq_cnt:U3\|freq\[25\] 3 REG LCFF_X9_Y13_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.499 ns; Loc. = LCFF_X9_Y13_N29; Fanout = 1; REG Node = 'freq_cnt:U3\|freq\[25\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { freq_cnt:U3|freq~1216 freq_cnt:U3|freq[25] } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_dev/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.460 ns ( 41.73 % ) " "Info: Total cell delay = 1.460 ns ( 41.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.039 ns ( 58.27 % ) " "Info: Total interconnect delay = 2.039 ns ( 58.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.499 ns" { reset freq_cnt:U3|freq~1216 freq_cnt:U3|freq[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.499 ns" { reset reset~combout freq_cnt:U3|freq~1216 freq_cnt:U3|freq[25] } { 0.000ns 0.000ns 2.039ns 0.000ns } { 0.000ns 1.150ns 0.202ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl freq_cnt:U3|freq[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.849 ns" { clk clk~combout clk~clkctrl freq_cnt:U3|freq[25] } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.499 ns" { reset freq_cnt:U3|freq~1216 freq_cnt:U3|freq[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.499 ns" { reset reset~combout freq_cnt:U3|freq~1216 freq_cnt:U3|freq[25] } { 0.000ns 0.000ns 2.039ns 0.000ns } { 0.000ns 1.150ns 0.202ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 09 22:19:42 2008 " "Info: Processing ended: Mon Jun 09 22:19:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}