📄 freq_dev.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count_int\[0\] register cycle\[24\]~reg0 169.66 MHz 5.894 ns Internal " "Info: Clock \"clk\" has Internal fmax of 169.66 MHz between source register \"count_int\[0\]\" and destination register \"cycle\[24\]~reg0\" (period= 5.894 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.629 ns + Longest register register " "Info: + Longest register to register delay is 5.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_int\[0\] 1 REG LCFF_X7_Y14_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y14_N3; Fanout = 2; REG Node = 'count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count_int[0] } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.596 ns) 1.024 ns Add0~325 2 COMB LCCOMB_X7_Y14_N6 2 " "Info: 2: + IC(0.428 ns) + CELL(0.596 ns) = 1.024 ns; Loc. = LCCOMB_X7_Y14_N6; Fanout = 2; COMB Node = 'Add0~325'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.024 ns" { count_int[0] Add0~325 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.110 ns Add0~327 3 COMB LCCOMB_X7_Y14_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.110 ns; Loc. = LCCOMB_X7_Y14_N8; Fanout = 2; COMB Node = 'Add0~327'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~325 Add0~327 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.196 ns Add0~329 4 COMB LCCOMB_X7_Y14_N10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.196 ns; Loc. = LCCOMB_X7_Y14_N10; Fanout = 2; COMB Node = 'Add0~329'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~327 Add0~329 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.282 ns Add0~331 5 COMB LCCOMB_X7_Y14_N12 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.282 ns; Loc. = LCCOMB_X7_Y14_N12; Fanout = 2; COMB Node = 'Add0~331'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~329 Add0~331 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.472 ns Add0~333 6 COMB LCCOMB_X7_Y14_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.190 ns) = 1.472 ns; Loc. = LCCOMB_X7_Y14_N14; Fanout = 2; COMB Node = 'Add0~333'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~331 Add0~333 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.558 ns Add0~335 7 COMB LCCOMB_X7_Y14_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.558 ns; Loc. = LCCOMB_X7_Y14_N16; Fanout = 2; COMB Node = 'Add0~335'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~333 Add0~335 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.644 ns Add0~337 8 COMB LCCOMB_X7_Y14_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.644 ns; Loc. = LCCOMB_X7_Y14_N18; Fanout = 2; COMB Node = 'Add0~337'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~335 Add0~337 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.730 ns Add0~339 9 COMB LCCOMB_X7_Y14_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.730 ns; Loc. = LCCOMB_X7_Y14_N20; Fanout = 2; COMB Node = 'Add0~339'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~337 Add0~339 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.816 ns Add0~341 10 COMB LCCOMB_X7_Y14_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.816 ns; Loc. = LCCOMB_X7_Y14_N22; Fanout = 2; COMB Node = 'Add0~341'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~339 Add0~341 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.902 ns Add0~343 11 COMB LCCOMB_X7_Y14_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 1.902 ns; Loc. = LCCOMB_X7_Y14_N24; Fanout = 2; COMB Node = 'Add0~343'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~341 Add0~343 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.988 ns Add0~345 12 COMB LCCOMB_X7_Y14_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 1.988 ns; Loc. = LCCOMB_X7_Y14_N26; Fanout = 2; COMB Node = 'Add0~345'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~343 Add0~345 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.074 ns Add0~347 13 COMB LCCOMB_X7_Y14_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.074 ns; Loc. = LCCOMB_X7_Y14_N28; Fanout = 2; COMB Node = 'Add0~347'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~345 Add0~347 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.249 ns Add0~349 14 COMB LCCOMB_X7_Y14_N30 2 " "Info: 14: + IC(0.000 ns) + CELL(0.175 ns) = 2.249 ns; Loc. = LCCOMB_X7_Y14_N30; Fanout = 2; COMB Node = 'Add0~349'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.175 ns" { Add0~347 Add0~349 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.335 ns Add0~351 15 COMB LCCOMB_X7_Y13_N0 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.335 ns; Loc. = LCCOMB_X7_Y13_N0; Fanout = 2; COMB Node = 'Add0~351'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~349 Add0~351 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.421 ns Add0~353 16 COMB LCCOMB_X7_Y13_N2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.421 ns; Loc. = LCCOMB_X7_Y13_N2; Fanout = 2; COMB Node = 'Add0~353'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~351 Add0~353 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.507 ns Add0~355 17 COMB LCCOMB_X7_Y13_N4 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.507 ns; Loc. = LCCOMB_X7_Y13_N4; Fanout = 2; COMB Node = 'Add0~355'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~353 Add0~355 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.593 ns Add0~357 18 COMB LCCOMB_X7_Y13_N6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.593 ns; Loc. = LCCOMB_X7_Y13_N6; Fanout = 2; COMB Node = 'Add0~357'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~355 Add0~357 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.679 ns Add0~359 19 COMB LCCOMB_X7_Y13_N8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.679 ns; Loc. = LCCOMB_X7_Y13_N8; Fanout = 2; COMB Node = 'Add0~359'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~357 Add0~359 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.765 ns Add0~361 20 COMB LCCOMB_X7_Y13_N10 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.765 ns; Loc. = LCCOMB_X7_Y13_N10; Fanout = 2; COMB Node = 'Add0~361'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~359 Add0~361 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.851 ns Add0~363 21 COMB LCCOMB_X7_Y13_N12 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 2.851 ns; Loc. = LCCOMB_X7_Y13_N12; Fanout = 2; COMB Node = 'Add0~363'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~361 Add0~363 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.041 ns Add0~365 22 COMB LCCOMB_X7_Y13_N14 2 " "Info: 22: + IC(0.000 ns) + CELL(0.190 ns) = 3.041 ns; Loc. = LCCOMB_X7_Y13_N14; Fanout = 2; COMB Node = 'Add0~365'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~363 Add0~365 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.127 ns Add0~367 23 COMB LCCOMB_X7_Y13_N16 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.127 ns; Loc. = LCCOMB_X7_Y13_N16; Fanout = 2; COMB Node = 'Add0~367'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~365 Add0~367 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.213 ns Add0~369 24 COMB LCCOMB_X7_Y13_N18 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.213 ns; Loc. = LCCOMB_X7_Y13_N18; Fanout = 2; COMB Node = 'Add0~369'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~367 Add0~369 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.299 ns Add0~371 25 COMB LCCOMB_X7_Y13_N20 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.299 ns; Loc. = LCCOMB_X7_Y13_N20; Fanout = 2; COMB Node = 'Add0~371'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~369 Add0~371 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.805 ns Add0~372 26 COMB LCCOMB_X7_Y13_N22 2 " "Info: 26: + IC(0.000 ns) + CELL(0.506 ns) = 3.805 ns; Loc. = LCCOMB_X7_Y13_N22; Fanout = 2; COMB Node = 'Add0~372'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~371 Add0~372 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.206 ns) 5.521 ns cycle~1222 27 COMB LCCOMB_X6_Y14_N20 1 " "Info: 27: + IC(1.510 ns) + CELL(0.206 ns) = 5.521 ns; Loc. = LCCOMB_X6_Y14_N20; Fanout = 1; COMB Node = 'cycle~1222'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.716 ns" { Add0~372 cycle~1222 } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.629 ns cycle\[24\]~reg0 28 REG LCFF_X6_Y14_N21 1 " "Info: 28: + IC(0.000 ns) + CELL(0.108 ns) = 5.629 ns; Loc. = LCFF_X6_Y14_N21; Fanout = 1; REG Node = 'cycle\[24\]~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { cycle~1222 cycle[24]~reg0 } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.691 ns ( 65.57 % ) " "Info: Total cell delay = 3.691 ns ( 65.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.938 ns ( 34.43 % ) " "Info: Total interconnect delay = 1.938 ns ( 34.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.629 ns" { count_int[0] Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~363 Add0~365 Add0~367 Add0~369 Add0~371 Add0~372 cycle~1222 cycle[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.629 ns" { count_int[0] Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~363 Add0~365 Add0~367 Add0~369 Add0~371 Add0~372 cycle~1222 cycle[24]~reg0 } { 0.000ns 0.428ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.510ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.858 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 192 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 192; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.913 ns) + CELL(0.666 ns) 2.858 ns cycle\[24\]~reg0 3 REG LCFF_X6_Y14_N21 1 " "Info: 3: + IC(0.913 ns) + CELL(0.666 ns) = 2.858 ns; Loc. = LCFF_X6_Y14_N21; Fanout = 1; REG Node = 'cycle\[24\]~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.579 ns" { clk~clkctrl cycle[24]~reg0 } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.19 % ) " "Info: Total cell delay = 1.806 ns ( 63.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.052 ns ( 36.81 % ) " "Info: Total interconnect delay = 1.052 ns ( 36.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.858 ns" { clk clk~clkctrl cycle[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.858 ns" { clk clk~combout clk~clkctrl cycle[24]~reg0 } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.859 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 192 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 192; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.666 ns) 2.859 ns count_int\[0\] 3 REG LCFF_X7_Y14_N3 2 " "Info: 3: + IC(0.914 ns) + CELL(0.666 ns) = 2.859 ns; Loc. = LCFF_X7_Y14_N3; Fanout = 2; REG Node = 'count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl count_int[0] } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.17 % ) " "Info: Total cell delay = 1.806 ns ( 63.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.053 ns ( 36.83 % ) " "Info: Total interconnect delay = 1.053 ns ( 36.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.858 ns" { clk clk~clkctrl cycle[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.858 ns" { clk clk~combout clk~clkctrl cycle[24]~reg0 } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 88 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.629 ns" { count_int[0] Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~363 Add0~365 Add0~367 Add0~369 Add0~371 Add0~372 cycle~1222 cycle[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.629 ns" { count_int[0] Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~363 Add0~365 Add0~367 Add0~369 Add0~371 Add0~372 cycle~1222 cycle[24]~reg0 } { 0.000ns 0.428ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.510ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.858 ns" { clk clk~clkctrl cycle[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.858 ns" { clk clk~combout clk~clkctrl cycle[24]~reg0 } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "detect_high:U2\|count_int\[0\] signel clk 6.161 ns register " "Info: tsu for register \"detect_high:U2\|count_int\[0\]\" (data pin = \"signel\", clock pin = \"clk\") is 6.161 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.066 ns + Longest pin register " "Info: + Longest pin to register delay is 9.066 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns signel 1 PIN PIN_130 32 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_130; Fanout = 32; PIN Node = 'signel'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signel } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.570 ns) + CELL(0.624 ns) 4.344 ns detect_high:U2\|count_int\[0\]~285 2 COMB LCCOMB_X9_Y5_N24 27 " "Info: 2: + IC(2.570 ns) + CELL(0.624 ns) = 4.344 ns; Loc. = LCCOMB_X9_Y5_N24; Fanout = 27; COMB Node = 'detect_high:U2\|count_int\[0\]~285'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.194 ns" { signel detect_high:U2|count_int[0]~285 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.062 ns) + CELL(0.660 ns) 9.066 ns detect_high:U2\|count_int\[0\] 3 REG LCFF_X25_Y17_N7 3 " "Info: 3: + IC(4.062 ns) + CELL(0.660 ns) = 9.066 ns; Loc. = LCFF_X25_Y17_N7; Fanout = 3; REG Node = 'detect_high:U2\|count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.722 ns" { detect_high:U2|count_int[0]~285 detect_high:U2|count_int[0] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.434 ns ( 26.85 % ) " "Info: Total cell delay = 2.434 ns ( 26.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.632 ns ( 73.15 % ) " "Info: Total interconnect delay = 6.632 ns ( 73.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.066 ns" { signel detect_high:U2|count_int[0]~285 detect_high:U2|count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.066 ns" { signel signel~combout detect_high:U2|count_int[0]~285 detect_high:U2|count_int[0] } { 0.000ns 0.000ns 2.570ns 4.062ns } { 0.000ns 1.150ns 0.624ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.865 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 192 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 192; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_dev.vhd" "" { Text "E:/tool_stud/freq_dev/freq_dev.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns detect_high:U2\|count_int\[0\] 3 REG LCFF_X25_Y17_N7 3 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X25_Y17_N7; Fanout = 3; REG Node = 'detect_high:U2\|count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl detect_high:U2|count_int[0] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/freq_dev/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl detect_high:U2|count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~combout clk~clkctrl detect_high:U2|count_int[0] } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.066 ns" { signel detect_high:U2|count_int[0]~285 detect_high:U2|count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.066 ns" { signel signel~combout detect_high:U2|count_int[0]~285 detect_high:U2|count_int[0] } { 0.000ns 0.000ns 2.570ns 4.062ns } { 0.000ns 1.150ns 0.624ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl detect_high:U2|count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~combout clk~clkctrl detect_high:U2|count_int[0] } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -