freq_dev.hier_info

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析

|freq_dev
clk => freq_cnt:U3.clk
clk => detect_high:U2.clk
clk => count:U1.clk
clk => cycle[0]~reg0.CLK
clk => cycle[1]~reg0.CLK
clk => cycle[2]~reg0.CLK
clk => cycle[3]~reg0.CLK
clk => cycle[4]~reg0.CLK
clk => cycle[5]~reg0.CLK
clk => cycle[6]~reg0.CLK
clk => cycle[7]~reg0.CLK
clk => cycle[8]~reg0.CLK
clk => cycle[9]~reg0.CLK
clk => cycle[10]~reg0.CLK
clk => cycle[11]~reg0.CLK
clk => cycle[12]~reg0.CLK
clk => cycle[13]~reg0.CLK
clk => cycle[14]~reg0.CLK
clk => cycle[15]~reg0.CLK
clk => cycle[16]~reg0.CLK
clk => cycle[17]~reg0.CLK
clk => cycle[18]~reg0.CLK
clk => cycle[19]~reg0.CLK
clk => cycle[20]~reg0.CLK
clk => cycle[21]~reg0.CLK
clk => cycle[22]~reg0.CLK
clk => cycle[23]~reg0.CLK
clk => cycle[24]~reg0.CLK
clk => cycle[25]~reg0.CLK
clk => cycle[26]~reg0.CLK
clk => count_int[0].CLK
clk => count_int[1].CLK
clk => count_int[2].CLK
clk => count_int[3].CLK
clk => count_int[4].CLK
clk => count_int[5].CLK
clk => count_int[6].CLK
clk => count_int[7].CLK
clk => count_int[8].CLK
clk => count_int[9].CLK
clk => count_int[10].CLK
clk => count_int[11].CLK
clk => count_int[12].CLK
clk => count_int[13].CLK
clk => count_int[14].CLK
clk => count_int[15].CLK
clk => count_int[16].CLK
clk => count_int[17].CLK
clk => count_int[18].CLK
clk => count_int[19].CLK
clk => count_int[20].CLK
clk => count_int[21].CLK
clk => count_int[22].CLK
clk => count_int[23].CLK
clk => count_int[24].CLK
clk => count_int[25].CLK
clk => count_int[26].CLK
clk => signel_buf.CLK
reset => count_int~27.OUTPUTSELECT
reset => count_int~28.OUTPUTSELECT
reset => count_int~29.OUTPUTSELECT
reset => count_int~30.OUTPUTSELECT
reset => count_int~31.OUTPUTSELECT
reset => count_int~32.OUTPUTSELECT
reset => count_int~33.OUTPUTSELECT
reset => count_int~34.OUTPUTSELECT
reset => count_int~35.OUTPUTSELECT
reset => count_int~36.OUTPUTSELECT
reset => count_int~37.OUTPUTSELECT
reset => count_int~38.OUTPUTSELECT
reset => count_int~39.OUTPUTSELECT
reset => count_int~40.OUTPUTSELECT
reset => count_int~41.OUTPUTSELECT
reset => count_int~42.OUTPUTSELECT
reset => count_int~43.OUTPUTSELECT
reset => count_int~44.OUTPUTSELECT
reset => count_int~45.OUTPUTSELECT
reset => count_int~46.OUTPUTSELECT
reset => count_int~47.OUTPUTSELECT
reset => count_int~48.OUTPUTSELECT
reset => count_int~49.OUTPUTSELECT
reset => count_int~50.OUTPUTSELECT
reset => count_int~51.OUTPUTSELECT
reset => count_int~52.OUTPUTSELECT
reset => count_int~53.OUTPUTSELECT
reset => cycle~27.OUTPUTSELECT
reset => cycle~28.OUTPUTSELECT
reset => cycle~29.OUTPUTSELECT
reset => cycle~30.OUTPUTSELECT
reset => cycle~31.OUTPUTSELECT
reset => cycle~32.OUTPUTSELECT
reset => cycle~33.OUTPUTSELECT
reset => cycle~34.OUTPUTSELECT
reset => cycle~35.OUTPUTSELECT
reset => cycle~36.OUTPUTSELECT
reset => cycle~37.OUTPUTSELECT
reset => cycle~38.OUTPUTSELECT
reset => cycle~39.OUTPUTSELECT
reset => cycle~40.OUTPUTSELECT
reset => cycle~41.OUTPUTSELECT
reset => cycle~42.OUTPUTSELECT
reset => cycle~43.OUTPUTSELECT
reset => cycle~44.OUTPUTSELECT
reset => cycle~45.OUTPUTSELECT
reset => cycle~46.OUTPUTSELECT
reset => cycle~47.OUTPUTSELECT
reset => cycle~48.OUTPUTSELECT
reset => cycle~49.OUTPUTSELECT
reset => cycle~50.OUTPUTSELECT
reset => cycle~51.OUTPUTSELECT
reset => cycle~52.OUTPUTSELECT
reset => cycle~53.OUTPUTSELECT
reset => freq_cnt:U3.reset
reset => detect_high:U2.reset
reset => count:U1.reset
signel => process2~0.IN1
signel => freq_cnt:U3.signel
signel => detect_high:U2.enable
signel => signel_buf.DATAIN
freq[0] <= freq_cnt:U3.freq[0]
freq[1] <= freq_cnt:U3.freq[1]
freq[2] <= freq_cnt:U3.freq[2]
freq[3] <= freq_cnt:U3.freq[3]
freq[4] <= freq_cnt:U3.freq[4]
freq[5] <= freq_cnt:U3.freq[5]
freq[6] <= freq_cnt:U3.freq[6]
freq[7] <= freq_cnt:U3.freq[7]
freq[8] <= freq_cnt:U3.freq[8]
freq[9] <= freq_cnt:U3.freq[9]
freq[10] <= freq_cnt:U3.freq[10]
freq[11] <= freq_cnt:U3.freq[11]
freq[12] <= freq_cnt:U3.freq[12]
freq[13] <= freq_cnt:U3.freq[13]
freq[14] <= freq_cnt:U3.freq[14]
freq[15] <= freq_cnt:U3.freq[15]
freq[16] <= freq_cnt:U3.freq[16]
freq[17] <= freq_cnt:U3.freq[17]
freq[18] <= freq_cnt:U3.freq[18]
freq[19] <= freq_cnt:U3.freq[19]
freq[20] <= freq_cnt:U3.freq[20]
freq[21] <= freq_cnt:U3.freq[21]
freq[22] <= freq_cnt:U3.freq[22]
freq[23] <= freq_cnt:U3.freq[23]
freq[24] <= freq_cnt:U3.freq[24]
freq[25] <= freq_cnt:U3.freq[25]
freq[26] <= freq_cnt:U3.freq[26]
cycle[0] <= cycle[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[1] <= cycle[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[2] <= cycle[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[3] <= cycle[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[4] <= cycle[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[5] <= cycle[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[6] <= cycle[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[7] <= cycle[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[8] <= cycle[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[9] <= cycle[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[10] <= cycle[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[11] <= cycle[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[12] <= cycle[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[13] <= cycle[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[14] <= cycle[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[15] <= cycle[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[16] <= cycle[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[17] <= cycle[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[18] <= cycle[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[19] <= cycle[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[20] <= cycle[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[21] <= cycle[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[22] <= cycle[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[23] <= cycle[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[24] <= cycle[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[25] <= cycle[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle[26] <= cycle[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Hwith[0] <= detect_high:U2.high_time[0]
Hwith[1] <= detect_high:U2.high_time[1]
Hwith[2] <= detect_high:U2.high_time[2]
Hwith[3] <= detect_high:U2.high_time[3]
Hwith[4] <= detect_high:U2.high_time[4]
Hwith[5] <= detect_high:U2.high_time[5]
Hwith[6] <= detect_high:U2.high_time[6]
Hwith[7] <= detect_high:U2.high_time[7]
Hwith[8] <= detect_high:U2.high_time[8]
Hwith[9] <= detect_high:U2.high_time[9]
Hwith[10] <= detect_high:U2.high_time[10]
Hwith[11] <= detect_high:U2.high_time[11]
Hwith[12] <= detect_high:U2.high_time[12]
Hwith[13] <= detect_high:U2.high_time[13]
Hwith[14] <= detect_high:U2.high_time[14]
Hwith[15] <= detect_high:U2.high_time[15]
Hwith[16] <= detect_high:U2.high_time[16]
Hwith[17] <= detect_high:U2.high_time[17]
Hwith[18] <= detect_high:U2.high_time[18]
Hwith[19] <= detect_high:U2.high_time[19]
Hwith[20] <= detect_high:U2.high_time[20]
Hwith[21] <= detect_high:U2.high_time[21]
Hwith[22] <= detect_high:U2.high_time[22]
Hwith[23] <= detect_high:U2.high_time[23]
Hwith[24] <= detect_high:U2.high_time[24]
Hwith[25] <= detect_high:U2.high_time[25]
Hwith[26] <= detect_high:U2.high_time[26]


|freq_dev|count:U1
clk => plus_1s~reg0.CLK
clk => count_int[0].CLK
clk => count_int[1].CLK
clk => count_int[2].CLK
clk => count_int[3].CLK
clk => count_int[4].CLK
clk => count_int[5].CLK
clk => count_int[6].CLK
clk => count_int[7].CLK
clk => count_int[8].CLK
clk => count_int[9].CLK
clk => count_int[10].CLK
clk => count_int[11].CLK
clk => count_int[12].CLK
clk => count_int[13].CLK
clk => count_int[14].CLK
clk => count_int[15].CLK
clk => count_int[16].CLK
clk => count_int[17].CLK
clk => count_int[18].CLK
clk => count_int[19].CLK
clk => count_int[20].CLK
clk => count_int[21].CLK
clk => count_int[22].CLK
clk => count_int[23].CLK
clk => count_int[24].CLK
clk => count_int[25].CLK
clk => count_int[26].CLK
reset => count_int~27.OUTPUTSELECT
reset => count_int~28.OUTPUTSELECT
reset => count_int~29.OUTPUTSELECT
reset => count_int~30.OUTPUTSELECT
reset => count_int~31.OUTPUTSELECT
reset => count_int~32.OUTPUTSELECT
reset => count_int~33.OUTPUTSELECT
reset => count_int~34.OUTPUTSELECT
reset => count_int~35.OUTPUTSELECT
reset => count_int~36.OUTPUTSELECT
reset => count_int~37.OUTPUTSELECT
reset => count_int~38.OUTPUTSELECT
reset => count_int~39.OUTPUTSELECT
reset => count_int~40.OUTPUTSELECT
reset => count_int~41.OUTPUTSELECT
reset => count_int~42.OUTPUTSELECT
reset => count_int~43.OUTPUTSELECT
reset => count_int~44.OUTPUTSELECT
reset => count_int~45.OUTPUTSELECT
reset => count_int~46.OUTPUTSELECT
reset => count_int~47.OUTPUTSELECT
reset => count_int~48.OUTPUTSELECT
reset => count_int~49.OUTPUTSELECT
reset => count_int~50.OUTPUTSELECT
reset => count_int~51.OUTPUTSELECT
reset => count_int~52.OUTPUTSELECT
reset => count_int~53.OUTPUTSELECT
reset => plus_1s~0.OUTPUTSELECT
plus_1s <= plus_1s~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freq_dev|detect_high:U2
clk => high_time[0]~reg0.CLK
clk => high_time[1]~reg0.CLK
clk => high_time[2]~reg0.CLK
clk => high_time[3]~reg0.CLK
clk => high_time[4]~reg0.CLK
clk => high_time[5]~reg0.CLK
clk => high_time[6]~reg0.CLK
clk => high_time[7]~reg0.CLK
clk => high_time[8]~reg0.CLK
clk => high_time[9]~reg0.CLK
clk => high_time[10]~reg0.CLK
clk => high_time[11]~reg0.CLK
clk => high_time[12]~reg0.CLK
clk => high_time[13]~reg0.CLK
clk => high_time[14]~reg0.CLK
clk => high_time[15]~reg0.CLK
clk => high_time[16]~reg0.CLK
clk => high_time[17]~reg0.CLK
clk => high_time[18]~reg0.CLK
clk => high_time[19]~reg0.CLK
clk => high_time[20]~reg0.CLK
clk => high_time[21]~reg0.CLK
clk => high_time[22]~reg0.CLK
clk => high_time[23]~reg0.CLK