📄 freq_dev.sim.rpt
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; |freq_dev|count:U1|count_int[9]~259 ; |freq_dev|count:U1|count_int[9]~483 ; cout ;
; |freq_dev|count:U1|count_int[10]~260 ; |freq_dev|count:U1|count_int[10]~260 ; combout ;
; |freq_dev|count:U1|count_int[10]~260 ; |freq_dev|count:U1|count_int[10]~484 ; cout ;
; |freq_dev|count:U1|count_int[11]~261 ; |freq_dev|count:U1|count_int[11]~261 ; combout ;
; |freq_dev|count:U1|count_int[11]~261 ; |freq_dev|count:U1|count_int[11]~485 ; cout ;
; |freq_dev|count:U1|count_int[12]~262 ; |freq_dev|count:U1|count_int[12]~262 ; combout ;
; |freq_dev|count:U1|count_int[12]~262 ; |freq_dev|count:U1|count_int[12]~486 ; cout ;
; |freq_dev|count:U1|count_int[13]~263 ; |freq_dev|count:U1|count_int[13]~263 ; combout ;
; |freq_dev|count:U1|count_int[13]~263 ; |freq_dev|count:U1|count_int[13]~487 ; cout ;
; |freq_dev|count:U1|count_int[14]~264 ; |freq_dev|count:U1|count_int[14]~264 ; combout ;
; |freq_dev|count:U1|count_int[14]~264 ; |freq_dev|count:U1|count_int[14]~488 ; cout ;
; |freq_dev|count:U1|count_int[15]~265 ; |freq_dev|count:U1|count_int[15]~265 ; combout ;
; |freq_dev|count:U1|count_int[15]~265 ; |freq_dev|count:U1|count_int[15]~489 ; cout ;
; |freq_dev|count:U1|count_int[16]~266 ; |freq_dev|count:U1|count_int[16]~266 ; combout ;
; |freq_dev|clk ; |freq_dev|clk ; combout ;
; |freq_dev|signel ; |freq_dev|signel ; combout ;
; |freq_dev|cycle[1] ; |freq_dev|cycle[1] ; padio ;
; |freq_dev|cycle[3] ; |freq_dev|cycle[3] ; padio ;
; |freq_dev|clk~clkctrl ; |freq_dev|clk~clkctrl ; outclk ;
+--------------------------------------------+--------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------------------+--------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------+--------------------------------------------+------------------+
; |freq_dev|freq_cnt:U3|freq[0] ; |freq_dev|freq_cnt:U3|freq[0] ; regout ;
; |freq_dev|freq_cnt:U3|freq[1] ; |freq_dev|freq_cnt:U3|freq[1] ; regout ;
; |freq_dev|freq_cnt:U3|freq[2] ; |freq_dev|freq_cnt:U3|freq[2] ; regout ;
; |freq_dev|freq_cnt:U3|freq[4] ; |freq_dev|freq_cnt:U3|freq[4] ; regout ;
; |freq_dev|freq_cnt:U3|freq[5] ; |freq_dev|freq_cnt:U3|freq[5] ; regout ;
; |freq_dev|freq_cnt:U3|freq[6] ; |freq_dev|freq_cnt:U3|freq[6] ; regout ;
; |freq_dev|freq_cnt:U3|freq[10] ; |freq_dev|freq_cnt:U3|freq[10] ; regout ;
; |freq_dev|freq_cnt:U3|freq[11] ; |freq_dev|freq_cnt:U3|freq[11] ; regout ;
; |freq_dev|freq_cnt:U3|freq[13] ; |freq_dev|freq_cnt:U3|freq[13] ; regout ;
; |freq_dev|freq_cnt:U3|freq[14] ; |freq_dev|freq_cnt:U3|freq[14] ; regout ;
; |freq_dev|freq_cnt:U3|freq[15] ; |freq_dev|freq_cnt:U3|freq[15] ; regout ;
; |freq_dev|freq_cnt:U3|freq[16] ; |freq_dev|freq_cnt:U3|freq[16] ; regout ;
; |freq_dev|freq_cnt:U3|freq[17] ; |freq_dev|freq_cnt:U3|freq[17] ; regout ;
; |freq_dev|freq_cnt:U3|freq[18] ; |freq_dev|freq_cnt:U3|freq[18] ; regout ;
; |freq_dev|freq_cnt:U3|freq[19] ; |freq_dev|freq_cnt:U3|freq[19] ; regout ;
; |freq_dev|freq_cnt:U3|freq[20] ; |freq_dev|freq_cnt:U3|freq[20] ; regout ;
; |freq_dev|freq_cnt:U3|freq[21] ; |freq_dev|freq_cnt:U3|freq[21] ; regout ;
; |freq_dev|freq_cnt:U3|freq[22] ; |freq_dev|freq_cnt:U3|freq[22] ; regout ;
; |freq_dev|freq_cnt:U3|freq[23] ; |freq_dev|freq_cnt:U3|freq[23] ; regout ;
; |freq_dev|freq_cnt:U3|freq[24] ; |freq_dev|freq_cnt:U3|freq[24] ; regout ;
; |freq_dev|freq_cnt:U3|freq[25] ; |freq_dev|freq_cnt:U3|freq[25] ; regout ;
; |freq_dev|freq_cnt:U3|freq[26] ; |freq_dev|freq_cnt:U3|freq[26] ; regout ;
; |freq_dev|cycle[0]~reg0 ; |freq_dev|cycle[0]~reg0 ; regout ;
; |freq_dev|cycle[5]~reg0 ; |freq_dev|cycle[5]~reg0 ; regout ;
; |freq_dev|cycle[6]~reg0 ; |freq_dev|cycle[6]~reg0 ; regout ;
; |freq_dev|cycle[7]~reg0 ; |freq_dev|cycle[7]~reg0 ; regout ;
; |freq_dev|cycle[8]~reg0 ; |freq_dev|cycle[8]~reg0 ; regout ;
; |freq_dev|cycle[9]~reg0 ; |freq_dev|cycle[9]~reg0 ; regout ;
; |freq_dev|cycle[10]~reg0 ; |freq_dev|cycle[10]~reg0 ; regout ;
; |freq_dev|cycle[11]~reg0 ; |freq_dev|cycle[11]~reg0 ; regout ;
; |freq_dev|cycle[12]~reg0 ; |freq_dev|cycle[12]~reg0 ; regout ;
; |freq_dev|cycle[13]~reg0 ; |freq_dev|cycle[13]~reg0 ; regout ;
; |freq_dev|cycle[14]~reg0 ; |freq_dev|cycle[14]~reg0 ; regout ;
; |freq_dev|cycle[15]~reg0 ; |freq_dev|cycle[15]~reg0 ; regout ;
; |freq_dev|cycle[16]~reg0 ; |freq_dev|cycle[16]~reg0 ; regout ;
; |freq_dev|cycle[17]~reg0 ; |freq_dev|cycle[17]~reg0 ; regout ;
; |freq_dev|cycle[18]~reg0 ; |freq_dev|cycle[18]~reg0 ; regout ;
; |freq_dev|cycle[19]~reg0 ; |freq_dev|cycle[19]~reg0 ; regout ;
; |freq_dev|cycle[20]~reg0 ; |freq_dev|cycle[20]~reg0 ; regout ;
; |freq_dev|cycle[21]~reg0 ; |freq_dev|cycle[21]~reg0 ; regout ;
; |freq_dev|cycle[22]~reg0 ; |freq_dev|cycle[22]~reg0 ; regout ;
; |freq_dev|cycle[23]~reg0 ; |freq_dev|cycle[23]~reg0 ; regout ;
; |freq_dev|cycle[24]~reg0 ; |freq_dev|cycle[24]~reg0 ; regout ;
; |freq_dev|cycle[25]~reg0 ; |freq_dev|cycle[25]~reg0 ; regout ;
; |freq_dev|cycle[26]~reg0 ; |freq_dev|cycle[26]~reg0 ; regout ;
; |freq_dev|detect_high:U2|high_time[0] ; |freq_dev|detect_high:U2|high_time[0] ; regout ;
; |freq_dev|detect_high:U2|high_time[2] ; |freq_dev|detect_high:U2|high_time[2] ; regout ;
; |freq_dev|detect_high:U2|high_time[4] ; |freq_dev|detect_high:U2|high_time[4] ; regout ;
; |freq_dev|detect_high:U2|high_time[5] ; |freq_dev|detect_high:U2|high_time[5] ; regout ;
; |freq_dev|detect_high:U2|high_time[6] ; |freq_dev|detect_high:U2|high_time[6] ; regout ;
; |freq_dev|detect_high:U2|high_time[7] ; |freq_dev|detect_high:U2|high_time[7] ; regout ;
; |freq_dev|detect_high:U2|high_time[8] ; |freq_dev|detect_high:U2|high_time[8] ; regout ;
; |freq_dev|detect_high:U2|high_time[9] ; |freq_dev|detect_high:U2|high_time[9] ; regout ;
; |freq_dev|detect_high:U2|high_time[10] ; |freq_dev|detect_high:U2|high_time[10] ; regout ;
; |freq_dev|detect_high:U2|high_time[11] ; |freq_dev|detect_high:U2|high_time[11] ; regout ;
; |freq_dev|detect_high:U2|high_time[12] ; |freq_dev|detect_high:U2|high_time[12] ; regout ;
; |freq_dev|detect_high:U2|high_time[13] ; |freq_dev|detect_high:U2|high_time[13] ; regout ;
; |freq_dev|detect_high:U2|high_time[14] ; |freq_dev|detect_high:U2|high_time[14] ; regout ;
; |freq_dev|detect_high:U2|high_time[15] ; |freq_dev|detect_high:U2|high_time[15] ; regout ;
; |freq_dev|detect_high:U2|high_time[16] ; |freq_dev|detect_high:U2|high_time[16] ; regout ;
; |freq_dev|detect_high:U2|high_time[17] ; |freq_dev|detect_high:U2|high_time[17] ; regout ;
; |freq_dev|detect_high:U2|high_time[18] ; |freq_dev|detect_high:U2|high_time[18] ; regout ;
; |freq_dev|detect_high:U2|high_time[19] ; |freq_dev|detect_high:U2|high_time[19] ; regout ;
; |freq_dev|detect_high:U2|high_time[20] ; |freq_dev|detect_high:U2|high_time[20] ; regout ;
; |freq_dev|detect_high:U2|high_time[21] ; |freq_dev|detect_high:U2|high_time[21] ; regout ;
; |freq_dev|detect_high:U2|high_time[22] ; |freq_dev|detect_high:U2|high_time[22] ; regout ;
; |freq_dev|detect_high:U2|high_time[23] ; |freq_dev|detect_high:U2|high_time[23] ; regout ;
; |freq_dev|detect_high:U2|high_time[24] ; |freq_dev|detect_high:U2|high_time[24] ; regout ;
; |freq_dev|detect_high:U2|high_time[25] ; |freq_dev|detect_high:U2|high_time[25] ; regout ;
; |freq_dev|detect_high:U2|high_time[26] ; |freq_dev|detect_high:U2|high_time[26] ; regout ;
; |freq_dev|freq_cnt:U3|count_int[13] ; |freq_dev|freq_cnt:U3|count_int[13] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1204 ; |freq_dev|freq_cnt:U3|freq~1204 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[14] ; |freq_dev|freq_cnt:U3|count_int[14] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1205 ; |freq_dev|freq_cnt:U3|freq~1205 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[15] ; |freq_dev|freq_cnt:U3|count_int[15] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1206 ; |freq_dev|freq_cnt:U3|freq~1206 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[16] ; |freq_dev|freq_cnt:U3|count_int[16] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1207 ; |freq_dev|freq_cnt:U3|freq~1207 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[17] ; |freq_dev|freq_cnt:U3|count_int[17] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1208 ; |freq_dev|freq_cnt:U3|freq~1208 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[18] ; |freq_dev|freq_cnt:U3|count_int[18] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1209 ; |freq_dev|freq_cnt:U3|freq~1209 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[19] ; |freq_dev|freq_cnt:U3|count_int[19] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1210 ; |freq_dev|freq_cnt:U3|freq~1210 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[20] ; |freq_dev|freq_cnt:U3|count_int[20] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1211 ; |freq_dev|freq_cnt:U3|freq~1211 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[21] ; |freq_dev|freq_cnt:U3|count_int[21] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1212 ; |freq_dev|freq_cnt:U3|freq~1212 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[22] ; |freq_dev|freq_cnt:U3|count_int[22] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1213 ; |freq_dev|freq_cnt:U3|freq~1213 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[23] ; |freq_dev|freq_cnt:U3|count_int[23] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1214 ; |freq_dev|freq_cnt:U3|freq~1214 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[24] ; |freq_dev|freq_cnt:U3|count_int[24] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1215 ; |freq_dev|freq_cnt:U3|freq~1215 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[25] ; |freq_dev|freq_cnt:U3|count_int[25] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1216 ; |freq_dev|freq_cnt:U3|freq~1216 ; combout ;
; |freq_dev|freq_cnt:U3|count_int[26] ; |freq_dev|freq_cnt:U3|count_int[26] ; regout ;
; |freq_dev|freq_cnt:U3|freq~1217 ; |freq_dev|freq_cnt:U3|freq~1217 ; combout ;
; |freq_dev|Add0~332 ; |freq_dev|Add0~333 ; cout ;
; |freq_dev|count_int[5] ; |freq_dev|count_int[5] ; regout ;
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