dianhuajifei.tan.qmsg

Verilog语言编写的电话计费系统

{ "Info" "ITDB_TH_RESULT" "money\[2\] decide\[2\] clk -5.137 ns register " "Info: th for register \"money\[2\]\" (data pin = \"decide\[2\]\", clock pin = \"clk\") is -5.137 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.211 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 88 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 88; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns money\[2\] 2 REG LC_X8_Y14_N7 8 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y14_N7; Fanout = 8; REG Node = 'money\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { clk money[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 money[2] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.363 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns decide\[2\] 1 PIN PIN_23 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 13; PIN Node = 'decide\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { decide[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.848 ns) + CELL(0.114 ns) 7.431 ns money\[2\]~4871 2 COMB LC_X8_Y14_N2 1 " "Info: 2: + IC(5.848 ns) + CELL(0.114 ns) = 7.431 ns; Loc. = LC_X8_Y14_N2; Fanout = 1; COMB Node = 'money\[2\]~4871'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.962 ns" { decide[2] money[2]~4871 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.478 ns) 8.363 ns money\[2\] 3 REG LC_X8_Y14_N7 8 " "Info: 3: + IC(0.454 ns) + CELL(0.478 ns) = 8.363 ns; Loc. = LC_X8_Y14_N7; Fanout = 8; REG Node = 'money\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.932 ns" { money[2]~4871 money[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.061 ns ( 24.64 % ) " "Info: Total cell delay = 2.061 ns ( 24.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.302 ns ( 75.36 % ) " "Info: Total interconnect delay = 6.302 ns ( 75.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.363 ns" { decide[2] money[2]~4871 money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.363 ns" { decide[2] decide[2]~out0 money[2]~4871 money[2] } { 0.000ns 0.000ns 5.848ns 0.454ns } { 0.000ns 1.469ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 money[2] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.363 ns" { decide[2] money[2]~4871 money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.363 ns" { decide[2] decide[2]~out0 money[2]~4871 money[2] } { 0.000ns 0.000ns 5.848ns 0.454ns } { 0.000ns 1.469ns 0.114ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 30 11:50:01 2008 " "Info: Processing ended: Sat Aug 30 11:50:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}