dianhuajifei.tan.qmsg

Verilog语言编写的电话计费系统

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register t1m register write~reg0 135.06 MHz 7.404 ns Internal " "Info: Clock \"clk\" has Internal fmax of 135.06 MHz between source register \"t1m\" and destination register \"write~reg0\" (period= 7.404 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.441 ns + Longest register register " "Info: + Longest register to register delay is 3.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t1m 1 REG LC_X10_Y14_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y14_N9; Fanout = 3; REG Node = 't1m'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { t1m } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.149 ns) + CELL(0.114 ns) 1.263 ns money~4865 2 COMB LC_X10_Y14_N2 5 " "Info: 2: + IC(1.149 ns) + CELL(0.114 ns) = 1.263 ns; Loc. = LC_X10_Y14_N2; Fanout = 5; COMB Node = 'money~4865'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.263 ns" { t1m money~4865 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.292 ns) 2.674 ns money\[1\]~4868 3 COMB LC_X8_Y14_N6 4 " "Info: 3: + IC(1.119 ns) + CELL(0.292 ns) = 2.674 ns; Loc. = LC_X8_Y14_N6; Fanout = 4; COMB Node = 'money\[1\]~4868'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.411 ns" { money~4865 money[1]~4868 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.309 ns) 3.441 ns write~reg0 4 REG LC_X8_Y14_N3 2 " "Info: 4: + IC(0.458 ns) + CELL(0.309 ns) = 3.441 ns; Loc. = LC_X8_Y14_N3; Fanout = 2; REG Node = 'write~reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.767 ns" { money[1]~4868 write~reg0 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.715 ns ( 20.78 % ) " "Info: Total cell delay = 0.715 ns ( 20.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.726 ns ( 79.22 % ) " "Info: Total interconnect delay = 2.726 ns ( 79.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.441 ns" { t1m money~4865 money[1]~4868 write~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.441 ns" { t1m money~4865 money[1]~4868 write~reg0 } { 0.000ns 1.149ns 1.119ns 0.458ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.211 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 88 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 88; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns write~reg0 2 REG LC_X8_Y14_N3 2 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y14_N3; Fanout = 2; REG Node = 'write~reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { clk write~reg0 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk write~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 write~reg0 } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.211 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 88 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 88; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns t1m 2 REG LC_X10_Y14_N9 3 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X10_Y14_N9; Fanout = 3; REG Node = 't1m'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { clk t1m } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk t1m } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 t1m } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk write~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 write~reg0 } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk t1m } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 t1m } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 20 -1 0 } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.441 ns" { t1m money~4865 money[1]~4868 write~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.441 ns" { t1m money~4865 money[1]~4868 write~reg0 } { 0.000ns 1.149ns 1.119ns 0.458ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk write~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 write~reg0 } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk t1m } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 t1m } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dtime\[0\] decide\[1\] clk 8.947 ns register " "Info: tsu for register \"dtime\[0\]\" (data pin = \"decide\[1\]\", clock pin = \"clk\") is 8.947 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.121 ns + Longest pin register " "Info: + Longest pin to register delay is 12.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns decide\[1\] 1 PIN PIN_227 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_227; Fanout = 8; PIN Node = 'decide\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { decide[1] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.332 ns) + CELL(0.590 ns) 8.397 ns dtime\[1\]~2006 2 COMB LC_X9_Y13_N6 2 " "Info: 2: + IC(6.332 ns) + CELL(0.590 ns) = 8.397 ns; Loc. = LC_X9_Y13_N6; Fanout = 2; COMB Node = 'dtime\[1\]~2006'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.922 ns" { decide[1] dtime[1]~2006 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.535 ns) + CELL(0.590 ns) 10.522 ns dtime\[1\]~2010 3 COMB LC_X11_Y14_N8 4 " "Info: 3: + IC(1.535 ns) + CELL(0.590 ns) = 10.522 ns; Loc. = LC_X11_Y14_N8; Fanout = 4; COMB Node = 'dtime\[1\]~2010'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.125 ns" { dtime[1]~2006 dtime[1]~2010 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.867 ns) 12.121 ns dtime\[0\] 4 REG LC_X12_Y14_N6 6 " "Info: 4: + IC(0.732 ns) + CELL(0.867 ns) = 12.121 ns; Loc. = LC_X12_Y14_N6; Fanout = 6; REG Node = 'dtime\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.599 ns" { dtime[1]~2010 dtime[0] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.522 ns ( 29.06 % ) " "Info: Total cell delay = 3.522 ns ( 29.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.599 ns ( 70.94 % ) " "Info: Total interconnect delay = 8.599 ns ( 70.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.121 ns" { decide[1] dtime[1]~2006 dtime[1]~2010 dtime[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.121 ns" { decide[1] decide[1]~out0 dtime[1]~2006 dtime[1]~2010 dtime[0] } { 0.000ns 0.000ns 6.332ns 1.535ns 0.732ns } { 0.000ns 1.475ns 0.590ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.211 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 88 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 88; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns dtime\[0\] 2 REG LC_X12_Y14_N6 6 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X12_Y14_N6; Fanout = 6; REG Node = 'dtime\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { clk dtime[0] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk dtime[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 dtime[0] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.121 ns" { decide[1] dtime[1]~2006 dtime[1]~2010 dtime[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.121 ns" { decide[1] decide[1]~out0 dtime[1]~2006 dtime[1]~2010 dtime[0] } { 0.000ns 0.000ns 6.332ns 1.535ns 0.732ns } { 0.000ns 1.475ns 0.590ns 0.590ns 0.867ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk dtime[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 dtime[0] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dispmoney\[2\] money\[2\] 10.342 ns register " "Info: tco from clock \"clk\" to destination pin \"dispmoney\[2\]\" through register \"money\[2\]\" is 10.342 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.211 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 88 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 88; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns money\[2\] 2 REG LC_X8_Y14_N7 8 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y14_N7; Fanout = 8; REG Node = 'money\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { clk money[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 money[2] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.907 ns + Longest register pin " "Info: + Longest register to pin delay is 6.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns money\[2\] 1 REG LC_X8_Y14_N7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y14_N7; Fanout = 8; REG Node = 'money\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { money[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.442 ns) 1.767 ns dispmoney~123 2 COMB LC_X9_Y13_N8 1 " "Info: 2: + IC(1.325 ns) + CELL(0.442 ns) = 1.767 ns; Loc. = LC_X9_Y13_N8; Fanout = 1; COMB Node = 'dispmoney~123'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.767 ns" { money[2] dispmoney~123 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.032 ns) + CELL(2.108 ns) 6.907 ns dispmoney\[2\] 3 PIN PIN_73 0 " "Info: 3: + IC(3.032 ns) + CELL(2.108 ns) = 6.907 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'dispmoney\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.140 ns" { dispmoney~123 dispmoney[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.550 ns ( 36.92 % ) " "Info: Total cell delay = 2.550 ns ( 36.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.357 ns ( 63.08 % ) " "Info: Total interconnect delay = 4.357 ns ( 63.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.907 ns" { money[2] dispmoney~123 dispmoney[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.907 ns" { money[2] dispmoney~123 dispmoney[2] } { 0.000ns 1.325ns 3.032ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { clk money[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { clk clk~out0 money[2] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.907 ns" { money[2] dispmoney~123 dispmoney[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.907 ns" { money[2] dispmoney~123 dispmoney[2] } { 0.000ns 1.325ns 3.032ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "card dispmoney\[2\] 14.503 ns Longest " "Info: Longest tpd from source pin \"card\" to destination pin \"dispmoney\[2\]\" is 14.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns card 1 PIN PIN_219 22 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_219; Fanout = 22; PIN Node = 'card'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { card } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.596 ns) + CELL(0.292 ns) 9.363 ns dispmoney~123 2 COMB LC_X9_Y13_N8 1 " "Info: 2: + IC(7.596 ns) + CELL(0.292 ns) = 9.363 ns; Loc. = LC_X9_Y13_N8; Fanout = 1; COMB Node = 'dispmoney~123'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.888 ns" { card dispmoney~123 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.032 ns) + CELL(2.108 ns) 14.503 ns dispmoney\[2\] 3 PIN PIN_73 0 " "Info: 3: + IC(3.032 ns) + CELL(2.108 ns) = 14.503 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'dispmoney\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.140 ns" { dispmoney~123 dispmoney[2] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.875 ns ( 26.72 % ) " "Info: Total cell delay = 3.875 ns ( 26.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.628 ns ( 73.28 % ) " "Info: Total interconnect delay = 10.628 ns ( 73.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.503 ns" { card dispmoney~123 dispmoney[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "14.503 ns" { card card~out0 dispmoney~123 dispmoney[2] } { 0.000ns 0.000ns 7.596ns 3.032ns } { 0.000ns 1.475ns 0.292ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}