dianhuajifei.fit.qmsg

Verilog语言编写的电话计费系统

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.330 ns register register " "Info: Estimated most critical path is register to register delay of 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num1\[7\] 1 REG LAB_X12_Y11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y11; Fanout = 4; REG Node = 'num1\[7\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { num1[7] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.114 ns) 1.418 ns Equal0~353 2 COMB LAB_X12_Y12 1 " "Info: 2: + IC(1.304 ns) + CELL(0.114 ns) = 1.418 ns; Loc. = LAB_X12_Y12; Fanout = 1; COMB Node = 'Equal0~353'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.418 ns" { num1[7] Equal0~353 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.442 ns) 2.760 ns Equal0~356 3 COMB LAB_X12_Y13 1 " "Info: 3: + IC(0.900 ns) + CELL(0.442 ns) = 2.760 ns; Loc. = LAB_X12_Y13; Fanout = 1; COMB Node = 'Equal0~356'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.342 ns" { Equal0~353 Equal0~356 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 3.413 ns Equal0~362 4 COMB LAB_X12_Y13 2 " "Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 3.413 ns; Loc. = LAB_X12_Y13; Fanout = 2; COMB Node = 'Equal0~362'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal0~356 Equal0~362 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 4.066 ns num1\[14\]~334 5 COMB LAB_X12_Y13 32 " "Info: 5: + IC(0.539 ns) + CELL(0.114 ns) = 4.066 ns; Loc. = LAB_X12_Y13; Fanout = 32; COMB Node = 'num1\[14\]~334'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal0~362 num1[14]~334 } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(1.112 ns) 6.330 ns num1\[26\] 6 REG LAB_X12_Y9 4 " "Info: 6: + IC(1.152 ns) + CELL(1.112 ns) = 6.330 ns; Loc. = LAB_X12_Y9; Fanout = 4; REG Node = 'num1\[26\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.264 ns" { num1[14]~334 num1[26] } "NODE_NAME" } } { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.372 ns ( 37.47 % ) " "Info: Total cell delay = 2.372 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.958 ns ( 62.53 % ) " "Info: Total interconnect delay = 3.958 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.330 ns" { num1[7] Equal0~353 Equal0~356 Equal0~362 num1[14]~334 num1[26] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x10_y14 x20_y27 " "Info: The peak interconnect region extends from location x10_y14 to location x20_y27" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 30 11:49:52 2008 " "Info: Processing ended: Sat Aug 30 11:49:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.fit.smsg " "Info: Generated suppressed messages file D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}