📄 cicupsimo.mdl
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SourceBlock "allblocks_alteradspbuilder2/Logical Bit Ope"
"rator"
SourceType "Logical Bit Operator AlteraBlockset"
LogicalOperator "AND"
user_inputs "2"
}
Block {
BlockType Reference
Name "Output"
Ports [1, 1]
Position [347, 350, 363, 415]
Orientation "down"
ForegroundColor "blue"
NamePlacement "alternate"
SourceBlock "allblocks_alteradspbuilder2/Output"
SourceType "Output AlteraBlockset"
iofile "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSI"
"MO\\CICUpSIMO_Source1_Output.capture"
BusType "Single Bit"
bwl "8"
bwr "0"
externalType "Inferred"
PORTTYPE "Output"
}
Block {
BlockType SubSystem
Name "datasource"
Ports [0, 1, 1]
Position [270, 443, 445, 527]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "datasource"
Location [0, 84, 1140, 837]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Fcn
Name "Fcn1"
Position [165, 130, 225, 160]
Expr "floor(2^3*u)"
}
Block {
BlockType Sin
Name "Initial Sine Wave"
Ports [0, 1]
Position [345, 265, 375, 295]
SineType "Sample based"
Amplitude "2^6 -1"
Samples "32"
Offset "16"
SampleTime "clk"
}
Block {
BlockType Step
Name "Noise Inject"
Position [250, 210, 280, 240]
Time "2500*clk"
SampleTime "clk"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [310, 201, 355, 234]
RndMeth "Floor"
}
Block {
BlockType RandomNumber
Name "Random\nNumber"
Position [110, 130, 140, 160]
Variance "8"
SampleTime "clk"
}
Block {
BlockType Sin
Name "Sine Wave1"
Ports [0, 1]
Position [185, 205, 215, 235]
SineType "Sample based"
Samples "5"
SampleTime "clk"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [380, 205, 410, 235]
ShowName off
IconShape "round"
Inputs "|++"
Port {
PortNumber 1
Name "Inphase"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [250, 130, 280, 160]
ShowName off
IconShape "round"
Inputs "|++"
}
Block {
BlockType Outport
Name "dout0"
Position [545, 213, 575, 227]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Random\nNumber"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sine Wave1"
SrcPort 1
Points [0, -40; 45, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Noise Inject"
SrcPort 1
Points [0, 0]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [10, 0]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Initial Sine Wave"
SrcPort 1
Points [15, 0]
DstBlock "Sum"
DstPort 2
}
Line {
Name "Inphase"
Labels [0, 0]
SrcBlock "Sum"
SrcPort 1
DstBlock "dout0"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "din0"
Ports [1, 1]
Position [475, 477, 540, 493]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSI"
"MO\\CICUpSIMO_Source1_din0.salt"
BusType "Signed Integer"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
externalType "Inferred"
}
Block {
BlockType Outport
Name "outvalid"
Position [715, 263, 745, 277]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "d0"
Position [715, 493, 745, 507]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "sop"
Position [715, 173, 745, 187]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "eop"
Position [720, 213, 750, 227]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "out_ready"
SrcPort 1
Points [0, 0; 85, 0]
Branch {
Points [130, 0]
Branch {
Points [70, 0]
DstBlock "Logical Bit Operator1"
DstPort 2
}
Branch {
Points [-5, 0]
DstBlock "Output"
DstPort 1
}
}
Branch {
Points [-50, 0]
DstBlock "Counter"
DstPort 4
}
}
Line {
SrcBlock "Counter"
SrcPort 1
Points [0, 95]
DstBlock "Comparator"
DstPort 2
}
Line {
SrcBlock "Comparator"
SrcPort 1
DstBlock "Logical Bit Operator1"
DstPort 1
}
Line {
SrcBlock "GND"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Counter"
DstPort 1
}
Branch {
Points [0, 20]
Branch {
DstBlock "Counter"
DstPort 2
}
Branch {
DstBlock "Counter"
DstPort 3
}
}
}
Line {
SrcBlock "resetn"
SrcPort 1
DstBlock "Logical Bit Operator"
DstPort 1
}
Line {
SrcBlock "Logical Bit Operator1"
SrcPort 1
Points [100, 0]
Branch {
Points [0, 230]
DstBlock "Delay"
DstPort 2
}
Branch {
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "datasource"
SrcPort 1
DstBlock "din0"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "d0"
DstPort 1
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "outvalid"
DstPort 1
}
Branch {
Points [0, -50]
Branch {
Points [0, -40]
DstBlock "sop"
DstPort 1
}
Branch {
DstBlock "eop"
DstPort 1
}
}
}
Line {
SrcBlock "Logical Bit Operator"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Counter"
DstPort 5
}
Branch {
Points [0, 335; 430, 0]
DstBlock "Delay"
DstPort 3
}
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Comparator"
DstPort 1
}
Line {
SrcBlock "Output"
SrcPort 1
DstBlock "datasource"
DstPort enable
}
Line {
SrcBlock "din0"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
}
}
Block {
BlockType Step
Name "Step"
Position [25, 340, 55, 370]
Time "10*clk"
SampleTime "clk"
}
Block {
BlockType Terminator
Name "Terminator"
Position [1030, 450, 1050, 470]
}
Block {
BlockType Terminator
Name "Terminator1"
Position [1645, 410, 1665, 430]
}
Block {
BlockType Reference
Name "cic_clken"
Ports [1, 1]
Position [1345, 177, 1395, 193]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSIMO\\"
"CICUpSIMO_cic_clken.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
externalType "Inferred"
}
Block {
BlockType Reference
Name "cic_outready"
Ports [1, 1]
Position [1345, 387, 1395, 403]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSIMO\\"
"CICUpSIMO_cic_outready.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
externalType "Inferred"
}
Block {
BlockType Reference
Name "cic_v7_2"
Ports [8, 5]
Position [1415, 165, 1610, 450]
ForegroundColor "blue"
DropShadow on
SourceBlock "megacorefunctions_alteradspbuilder2/MegaCore"
SourceType "MegaCore AlteraBlockset"
entityName "cic_v7_2_import"
inNames "clken reset_n in_data in_startofpacket in_endof"
"packet in_valid out_ready in_error "
inBwls "1 1 16 1 1 1 1 2"
inBwrs "0 0 0 0 0 0 0 0"
inTypes "b b u b b b b u "
inDelayed "1 0 1 1 1 1 1 1"
outNames "out0_data out1_data in_ready out_valid out_erro"
"r "
outBwls "16 16 1 1 2"
outBwrs "0 0 0 0 0"
outTypes "u u b b u "
xmlmapfile "c:\\altera\\72\\quartus\\dsp_builder\\lib\\Simg"
"enCMap.xml"
launch_params "-parameterization.megawizard2:1 -hide_splash -"
"parameterization.activate_atstartup:1 -hide_iptb -parameterization.window_loc"
"ation:center -limitfiles"
is_megacore "on"
use_dynamic_feedthrough_data "on"
use_alphabetical_port_ordering "off"
vofile "DSPBuilder_CICUpSIMO_import\\cic_v7_2.vo"
n_input_port "8"
n_output_port "5"
core_dir "C:\\altera\\72\\ip\\cic\\lib\\ip_toolbench"
core_name "cic"
clockname "clk"
flow_dir "C:\\altera\\72\\ip\\cic\\lib\\../../common/ip_t"
"oolbench/v1.3.0/bin"
core_version "7.2"
NewVariation "off"
VhdlVariationDate "18-Jan-2008 17:13:04"
VhdlVariationName "C:\\DesignExample\\CIC_SIMO_v72\\DSPBuilder_CIC"
"UpSIMO_import\\cic_v7_2.vhd"
use_systemC_model "off"
wizard "cic"
inptype "bbubbbbu"
outptype "uubbu"
}
Block {
BlockType Reference
Name "fir_compiler_v7_2"
Ports [7, 7]
Position [780, 214, 1010, 526]
ForegroundColor "blue"
DropShadow on
SourceBlock "megacorefunctions_alteradspbuilder2/MegaCore"
SourceType "MegaCore AlteraBlockset"
entityName "fir_compiler_v7_2_import"
inNames "reset_n ast_sink_data ast_sink_valid ast_source"
"_ready ast_sink_sop ast_sink_eop ast_sink_error "
inBwls ⌨️ 快捷键说明
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