📄 cicupsimo.mdl
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MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "datasource"
Location [0, 84, 1140, 837]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Fcn
Name "Fcn1"
Position [165, 130, 225, 160]
Expr "floor(2^3*u)"
}
Block {
BlockType Sin
Name "Initial Sine Wave"
Ports [0, 1]
Position [345, 265, 375, 295]
SineType "Sample based"
Amplitude "2^6 -1"
Samples "32"
SampleTime "clk"
}
Block {
BlockType Step
Name "Noise Inject"
Position [250, 210, 280, 240]
Time "2500*clk"
SampleTime "clk"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [310, 201, 355, 234]
RndMeth "Floor"
}
Block {
BlockType RandomNumber
Name "Random\nNumber"
Position [110, 130, 140, 160]
Variance "8"
SampleTime "clk"
}
Block {
BlockType Sin
Name "Sine Wave1"
Ports [0, 1]
Position [185, 205, 215, 235]
SineType "Sample based"
Samples "5"
SampleTime "clk"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [380, 205, 410, 235]
ShowName off
IconShape "round"
Inputs "|++"
Port {
PortNumber 1
Name "Inphase"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [250, 130, 280, 160]
ShowName off
IconShape "round"
Inputs "|++"
}
Block {
BlockType Outport
Name "dout0"
Position [545, 213, 575, 227]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Random\nNumber"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sine Wave1"
SrcPort 1
Points [0, -40; 45, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Noise Inject"
SrcPort 1
Points [0, 0]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [10, 0]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Initial Sine Wave"
SrcPort 1
Points [15, 0]
DstBlock "Sum"
DstPort 2
}
Line {
Name "Inphase"
Labels [0, 0]
SrcBlock "Sum"
SrcPort 1
DstBlock "dout0"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "din0"
Ports [1, 1]
Position [475, 477, 540, 493]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSI"
"MO\\CICUpSIMO_Source0_din0.salt"
BusType "Signed Integer"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
externalType "Inferred"
}
Block {
BlockType Outport
Name "outvalid"
Position [715, 263, 745, 277]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "d0"
Position [715, 493, 745, 507]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "sop"
Position [715, 173, 745, 187]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "eop"
Position [720, 213, 750, 227]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "out_ready"
SrcPort 1
Points [0, 0; 85, 0]
Branch {
Points [130, 0]
Branch {
Points [70, 0]
DstBlock "Logical Bit Operator1"
DstPort 2
}
Branch {
Points [-5, 0]
DstBlock "Output"
DstPort 1
}
}
Branch {
Points [-50, 0]
DstBlock "Counter"
DstPort 4
}
}
Line {
SrcBlock "Counter"
SrcPort 1
Points [0, 95]
DstBlock "Comparator"
DstPort 2
}
Line {
SrcBlock "Comparator"
SrcPort 1
DstBlock "Logical Bit Operator1"
DstPort 1
}
Line {
SrcBlock "GND"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Counter"
DstPort 1
}
Branch {
Points [0, 20]
Branch {
DstBlock "Counter"
DstPort 2
}
Branch {
DstBlock "Counter"
DstPort 3
}
}
}
Line {
SrcBlock "resetn"
SrcPort 1
DstBlock "Logical Bit Operator"
DstPort 1
}
Line {
SrcBlock "Logical Bit Operator1"
SrcPort 1
Points [100, 0]
Branch {
Points [0, 230]
DstBlock "Delay"
DstPort 2
}
Branch {
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "datasource"
SrcPort 1
DstBlock "din0"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "d0"
DstPort 1
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "outvalid"
DstPort 1
}
Branch {
Points [0, -50]
Branch {
Points [0, -40]
DstBlock "sop"
DstPort 1
}
Branch {
DstBlock "eop"
DstPort 1
}
}
}
Line {
SrcBlock "Logical Bit Operator"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Counter"
DstPort 5
}
Branch {
Points [0, 335; 430, 0]
DstBlock "Delay"
DstPort 3
}
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Comparator"
DstPort 1
}
Line {
SrcBlock "Output"
SrcPort 1
DstBlock "datasource"
DstPort enable
}
Line {
SrcBlock "din0"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Source1"
Ports [2, 4]
Position [180, 385, 275, 530]
NamePlacement "alternate"
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Source1"
Location [2, 84, 1270, 997]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "out_ready"
Position [110, 318, 140, 332]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "resetn"
Position [45, 203, 75, 217]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "Comparator"
Ports [2, 1]
Position [385, 240, 415, 275]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Comparator"
SourceType "Comparator AlteraBlockset"
direction "a == b"
}
Block {
BlockType Reference
Name "Constant"
Ports [0, 1]
Position [330, 239, 365, 251]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Constant"
SourceType "Constant AlteraBlockset"
mask_cst "7"
BusType "Unsigned Integer"
bwl "4"
bwr "0"
roundMode "Truncate"
satMode "Wrap"
SpecifyClock off
clock "clk"
}
Block {
BlockType Reference
Name "Counter"
Ports [5, 1]
Position [195, 115, 315, 225]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Counter"
SourceType "Counter AlteraBlockset"
BusType "Unsigned Integer"
bwl "4"
bwr "0"
use_modulo on
modulo "8"
SpecifyClock off
direction "Use Direction Port (updown)"
use_sload on
use_sset off
svalue "1"
use_clk_ena on
use_ena off
use_sclr on
}
Block {
BlockType Reference
Name "Delay"
Ports [3, 1]
Position [605, 475, 650, 525]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Delay"
SourceType "Delay AlteraBlockset"
pipeline "1"
ClockPhase "1"
use_ena on
use_sclr on
use_init off
reset_value "1"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [610, 245, 655, 295]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Delay"
SourceType "Delay AlteraBlockset"
pipeline "1"
ClockPhase "1"
use_ena off
use_sclr off
use_init off
reset_value "1"
}
Block {
BlockType Reference
Name "GND"
Ports [0, 1]
Position [120, 122, 135, 138]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/GND"
SourceType "GND AlteraBlockset"
SpecifyClock off
}
Block {
BlockType Reference
Name "Logical Bit Operator"
Ports [1, 1]
Position [115, 191, 145, 229]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Logical Bit Ope"
"rator"
SourceType "Logical Bit Operator AlteraBlockset"
LogicalOperator "NOT"
user_inputs "2"
}
Block {
BlockType Reference
Name "Logical Bit Operator1"
Ports [2, 1]
Position [445, 251, 475, 289]
ForegroundColor "blue"
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