⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 cicupsimo.mdl

📁 用于dspbuilder 可以直接生成vhdl源码
💻 MDL
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
	  Name			  "in_err"
	  Ports			  [1, 1]
	  Position		  [75, 217, 140, 233]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Unsigned Integer"
	  bwl			  "2"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "in_ready"
	  Ports			  [1, 1]
	  Position		  [530, 137, 595, 153]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "in_sop"
	  Ports			  [1, 1]
	  Position		  [70, 252, 135, 268]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "in_valid"
	  Ports			  [1, 1]
	  Position		  [70, 177, 135, 193]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_data"
	  Ports			  [1, 1]
	  Position		  [510, 67, 575, 83]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Signed Integer"
	  bwl			  "16"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_eop"
	  Ports			  [1, 1]
	  Position		  [490, 327, 555, 343]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_err"
	  Ports			  [1, 1]
	  Position		  [520, 217, 585, 233]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Unsigned Integer"
	  bwl			  "2"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_ready"
	  Ports			  [1, 1]
	  Position		  [65, 137, 130, 153]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_sop"
	  Ports			  [1, 1]
	  Position		  [505, 252, 570, 268]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_valid"
	  Ports			  [1, 1]
	  Position		  [520, 177, 585, 193]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  saturate		  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "In_ready"
	  Position		  [620, 138, 650, 152]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_data[15:0]"
	  Position		  [600, 68, 630, 82]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_eop"
	  Position		  [580, 328, 610, 342]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_err[1:0]"
	  Position		  [610, 218, 640, 232]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_sop"
	  Position		  [595, 253, 625, 267]
	  ForegroundColor	  "blue"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_valid"
	  Position		  [610, 178, 640, 192]
	  ForegroundColor	  "blue"
	  Port			  "6"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In_data[25:0]"
	  SrcPort		  1
	  DstBlock		  "in_data"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Out_ready"
	  SrcPort		  1
	  DstBlock		  "out_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_valid"
	  SrcPort		  1
	  DstBlock		  "in_valid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_sop"
	  SrcPort		  1
	  DstBlock		  "in_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_eop"
	  SrcPort		  1
	  DstBlock		  "in_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_ready"
	  SrcPort		  1
	  DstBlock		  "In_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_valid"
	  SrcPort		  1
	  DstBlock		  "Out_valid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_sop"
	  SrcPort		  1
	  DstBlock		  "Out_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_eop"
	  SrcPort		  1
	  DstBlock		  "Out_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_data"
	  SrcPort		  1
	  DstBlock		  "Saturate"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_data"
	  SrcPort		  1
	  DstBlock		  "Out_data[15:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Saturate"
	  SrcPort		  1
	  DstBlock		  "Round"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Round"
	  SrcPort		  1
	  DstBlock		  "out_data"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_ready"
	  SrcPort		  1
	  DstBlock		  "in_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_sop"
	  SrcPort		  1
	  DstBlock		  "out_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_eop"
	  SrcPort		  1
	  DstBlock		  "out_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_valid"
	  SrcPort		  1
	  DstBlock		  "out_valid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_err[1:0]"
	  SrcPort		  1
	  DstBlock		  "in_err"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_err"
	  SrcPort		  1
	  DstBlock		  "out_err"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_err"
	  SrcPort		  1
	  DstBlock		  "Out_err[1:0]"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [504, 53, 573, 100]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder2/Signal Compiler"
      SourceType	      "Signal Compiler AlteraBlockset"
      DeviceFamily	      "Stratix II"
      DeviceName	      "AUTO"
      EnableSignalTap	      off
      SignalTapDepth	      "128"
      UseBoardBlock	      off
      StpUseDefaultClock      on
      StpClock		      "Clock"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Source0"
      Ports		      [2, 4]
      Position		      [180, 245, 275, 390]
      NamePlacement	      "alternate"
      TreatAsAtomicUnit	      on
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Source0"
	Location		[2, 84, 1270, 997]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "out_ready"
	  Position		  [110, 318, 140, 332]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "resetn"
	  Position		  [45, 203, 75, 217]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Comparator"
	  Ports			  [2, 1]
	  Position		  [385, 240, 415, 275]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Comparator"
	  SourceType		  "Comparator AlteraBlockset"
	  direction		  "a == b"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [330, 239, 365, 251]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Constant"
	  SourceType		  "Constant AlteraBlockset"
	  mask_cst		  "7"
	  BusType		  "Unsigned Integer"
	  bwl			  "4"
	  bwr			  "0"
	  roundMode		  "Truncate"
	  satMode		  "Wrap"
	  SpecifyClock		  off
	  clock			  "clk"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [5, 1]
	  Position		  [195, 115, 315, 225]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Counter"
	  SourceType		  "Counter AlteraBlockset"
	  BusType		  "Unsigned Integer"
	  bwl			  "4"
	  bwr			  "0"
	  use_modulo		  on
	  modulo		  "8"
	  SpecifyClock		  off
	  direction		  "Use Direction Port (updown)"
	  use_sload		  on
	  use_sset		  off
	  svalue		  "1"
	  use_clk_ena		  on
	  use_ena		  off
	  use_sclr		  on
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [3, 1]
	  Position		  [605, 475, 650, 525]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Delay"
	  SourceType		  "Delay AlteraBlockset"
	  pipeline		  "1"
	  ClockPhase		  "1"
	  use_ena		  on
	  use_sclr		  on
	  use_init		  off
	  reset_value		  "1"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay1"
	  Ports			  [1, 1]
	  Position		  [610, 245, 655, 295]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Delay"
	  SourceType		  "Delay AlteraBlockset"
	  pipeline		  "1"
	  ClockPhase		  "1"
	  use_ena		  off
	  use_sclr		  off
	  use_init		  off
	  reset_value		  "1"
	}
	Block {
	  BlockType		  Reference
	  Name			  "GND"
	  Ports			  [0, 1]
	  Position		  [120, 122, 135, 138]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/GND"
	  SourceType		  "GND AlteraBlockset"
	  SpecifyClock		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical Bit Operator"
	  Ports			  [1, 1]
	  Position		  [115, 191, 145, 229]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Logical Bit Ope"
"rator"
	  SourceType		  "Logical Bit Operator AlteraBlockset"
	  LogicalOperator	  "NOT"
	  user_inputs		  "2"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical Bit Operator1"
	  Ports			  [2, 1]
	  Position		  [445, 251, 475, 289]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Logical Bit Ope"
"rator"
	  SourceType		  "Logical Bit Operator AlteraBlockset"
	  LogicalOperator	  "AND"
	  user_inputs		  "2"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output"
	  Ports			  [1, 1]
	  Position		  [347, 350, 363, 415]
	  Orientation		  "down"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  SourceBlock		  "allblocks_alteradspbuilder2/Output"
	  SourceType		  "Output AlteraBlockset"
	  iofile		  "C:\\DesignExample\\CIC_SIMO_v72\\tb_CICUpSI"
"MO\\CICUpSIMO_Source0_Output.capture"
	  BusType		  "Single Bit"
	  bwl			  "8"
	  bwr			  "0"
	  externalType		  "Inferred"
	  PORTTYPE		  "Output"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "datasource"
	  Ports			  [0, 1, 1]
	  Position		  [270, 443, 445, 527]
	  TreatAsAtomicUnit	  on
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -