ps2.v

来自「在vhdl开发环境下」· Verilog 代码 · 共 83 行

module PS2
( 
  clk,     // system clk recommend 33MHz or higher;
  clkin,   // PS2 clk, come from mouse or keyboard;
  data,    // PS2 data;
  req,     // set 1 when there is data recieved;
  creq,    // set 1 to reset req to 0;
  rbufer   // data buffer, data recieved are kept in it; 
);

input clkin;
inout data;
input creq;
outout req;
output[7:0] rbuffer;

reg req;
reg[7:0] rbuffer;

reg[7:0] recv;
reg[3:0] m;

reg clkin_last;
reg req_p;

always@(posedge(clk))
begin
  clkin_last=clkin;
end

always@(posedge(clk))
begin
  case(m)
  0: begin
       if((clkin_last==1)&&(clkin==0)) begin
         if(data==0) m=1;
       end
     end
  1,2,3,4,5,6,7,8:
     begin
       if((clkin_last==1)&&(clkin==0)) begin
         recv=recv>>1;
         recv[7]=data;
         m=m+1;
       end
     end
  9: begin
       if((clkin_last==1)&&(clkin==0)) begin
         m=m+1;
       end
     end
  10:
     begin
       if((clkin_last==1)&&(clkin==0)) begin
         if(data==1) begin
           rbuffer=recv;
           req_p=1;
           m=m+1;
         end
       end
     end 
  11:
    begin
      req_p=0;
      m=0;
    end   
  default:
     begin
       m=0;
     end
  endcase   
end

always@(posedge(clk))
begin
  if(req_p==1) req=1;
  else if(creq==1) req=0;  
end

endmodule