📄 altsyncram_drg1.tdf
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OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 8,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a9 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 9,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a10 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 10,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a11 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 11,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a12 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 12,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a13 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 13,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a14 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 14,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block6a15 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "clear1",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 511,
PORT_A_LOGICAL_RAM_DEPTH = 512,
PORT_A_LOGICAL_RAM_WIDTH = 16,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 15,
PORT_B_LAST_ADDRESS = 511,
PORT_B_LOGICAL_RAM_DEPTH = 512,
PORT_B_LOGICAL_RAM_WIDTH = 16,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
address_a_wire[8..0] : WIRE;
address_b_wire[8..0] : WIRE;
BEGIN
ram_block6a[15..0].clk0 = clock0;
ram_block6a[15..0].clk1 = clock1;
ram_block6a[15..0].clr1 = aclr1;
ram_block6a[15..0].ena0 = clocken0;
ram_block6a[15..0].ena1 = clocken1;
ram_block6a[15..0].portaaddr[] = ( address_a_wire[8..0]);
ram_block6a[15..0].portaaddrstall = addressstall_a;
ram_block6a[0].portadatain[] = ( data_a[0..0]);
ram_block6a[1].portadatain[] = ( data_a[1..1]);
ram_block6a[2].portadatain[] = ( data_a[2..2]);
ram_block6a[3].portadatain[] = ( data_a[3..3]);
ram_block6a[4].portadatain[] = ( data_a[4..4]);
ram_block6a[5].portadatain[] = ( data_a[5..5]);
ram_block6a[6].portadatain[] = ( data_a[6..6]);
ram_block6a[7].portadatain[] = ( data_a[7..7]);
ram_block6a[8].portadatain[] = ( data_a[8..8]);
ram_block6a[9].portadatain[] = ( data_a[9..9]);
ram_block6a[10].portadatain[] = ( data_a[10..10]);
ram_block6a[11].portadatain[] = ( data_a[11..11]);
ram_block6a[12].portadatain[] = ( data_a[12..12]);
ram_block6a[13].portadatain[] = ( data_a[13..13]);
ram_block6a[14].portadatain[] = ( data_a[14..14]);
ram_block6a[15].portadatain[] = ( data_a[15..15]);
ram_block6a[15..0].portawe = wren_a;
ram_block6a[15..0].portbaddr[] = ( address_b_wire[8..0]);
ram_block6a[0].portbdatain[] = ( data_b[0..0]);
ram_block6a[1].portbdatain[] = ( data_b[1..1]);
ram_block6a[2].portbdatain[] = ( data_b[2..2]);
ram_block6a[3].portbdatain[] = ( data_b[3..3]);
ram_block6a[4].portbdatain[] = ( data_b[4..4]);
ram_block6a[5].portbdatain[] = ( data_b[5..5]);
ram_block6a[6].portbdatain[] = ( data_b[6..6]);
ram_block6a[7].portbdatain[] = ( data_b[7..7]);
ram_block6a[8].portbdatain[] = ( data_b[8..8]);
ram_block6a[9].portbdatain[] = ( data_b[9..9]);
ram_block6a[10].portbdatain[] = ( data_b[10..10]);
ram_block6a[11].portbdatain[] = ( data_b[11..11]);
ram_block6a[12].portbdatain[] = ( data_b[12..12]);
ram_block6a[13].portbdatain[] = ( data_b[13..13]);
ram_block6a[14].portbdatain[] = ( data_b[14..14]);
ram_block6a[15].portbdatain[] = ( data_b[15..15]);
ram_block6a[15..0].portbrewe = wren_b;
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_a[] = ( ram_block6a[15..0].portadataout[0..0]);
q_b[] = ( ram_block6a[15..0].portbdataout[0..0]);
END;
--VALID FILE
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