dcfifo_m2o1.tdf

在altera DE2 的开发板上采集图像

--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 8.0 cbx_a_gray2bin 2008:02:23:252825 cbx_a_graycounter 2008:02:23:252825 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_dcfifo 2008:04:22:277785 cbx_fifo_common 2008:02:23:252825 cbx_flex10ke 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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FUNCTION a_gray2bin_kdb (gray[9..0])
RETURNS ( bin[9..0]);
FUNCTION a_graycounter_o96 (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_fgc (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_egc (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION altsyncram_1l81 (aclr1, address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION dffpipe_ngh (clock, clrn, d[0..0])
RETURNS ( q[0..0]);
FUNCTION dffpipe_kec (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION alt_synch_pipe_qdb (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION dffpipe_oe9 (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION alt_synch_pipe_ud8 (clock, clrn, d[9..0])
RETURNS ( q[9..0]);

--synthesis_resources = lut 69 M4K 2 reg 115 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=s102;{-to p0addr} POWER_UP_LEVEL=LOW;{-to rdptr_g} suppress_da_rule_internal=r105;{ -from ""rdptr_g"" -to ""ws_dgrp|dffpipe11|dffe12a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_pe9:dffpipe11|dffe12a* "";{ -from ""delayed_wrptr_g"" -to ""rs_dgwp|dffpipe9|dffe10a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_oe9:dffpipe9|dffe10a* """;

SUBDESIGN dcfifo_m2o1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	rdusedw[8..0]	:	output;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[8..0]	:	output;
) 
VARIABLE 
	rdptr_g_gray2bin : a_gray2bin_kdb;
	rs_dgwp_gray2bin : a_gray2bin_kdb;
	wrptr_g_gray2bin : a_gray2bin_kdb;
	ws_dgrp_gray2bin : a_gray2bin_kdb;
	rdptr_g1p : a_graycounter_o96;
	wrptr_g1p : a_graycounter_fgc;
	wrptr_gp : a_graycounter_egc;
	fifo_ram : altsyncram_1l81;
	delayed_wrptr_g[9..0] : dffe;
	p0addr : dffe
		WITH (
			power_up = "low"
		);
	rdptr_g[9..0] : dffe;
	rdaclr : dffpipe_ngh;
	rs_brp : dffpipe_kec;
	rs_bwp : dffpipe_kec;
	rs_dgwp : alt_synch_pipe_qdb;
	ws_brp : dffpipe_oe9;
	ws_bwp : dffpipe_oe9;
	ws_dgrp : alt_synch_pipe_ud8;
	rdusedw_sub_dataa[9..0]	:	WIRE;
	rdusedw_sub_datab[9..0]	:	WIRE;
	rdusedw_sub_result[9..0]	:	WIRE;
	wrusedw_sub_dataa[9..0]	:	WIRE;
	wrusedw_sub_datab[9..0]	:	WIRE;
	wrusedw_sub_result[9..0]	:	WIRE;
	rdempty_eq_comp_aeb_int	:	WIRE;
	rdempty_eq_comp_aeb	:	WIRE;
	rdempty_eq_comp_dataa[9..0]	:	WIRE;
	rdempty_eq_comp_datab[9..0]	:	WIRE;
	wrfull_eq_comp_aeb_int	:	WIRE;
	wrfull_eq_comp_aeb	:	WIRE;
	wrfull_eq_comp_dataa[9..0]	:	WIRE;
	wrfull_eq_comp_datab[9..0]	:	WIRE;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[8..0]	: WIRE;
	ram_address_b[8..0]	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[9..0]	: WIRE;

BEGIN 
	rdptr_g_gray2bin.gray[9..0] = rdptr_g[9..0].q;
	rs_dgwp_gray2bin.gray[9..0] = rs_dgwp.q[9..0];
	wrptr_g_gray2bin.gray[9..0] = wrptr_gp.q[9..0];
	ws_dgrp_gray2bin.gray[9..0] = ws_dgrp.q[9..0];
	rdptr_g1p.aclr = (! rdaclr.q[]);
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.aclr = aclr;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.aclr1 = aclr;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].clrn = (! aclr);
	delayed_wrptr_g[].d = wrptr_gp.q[];
	p0addr.clk = rdclk;
	p0addr.clrn = rdaclr.q[];
	p0addr.d = B"1";
	rdptr_g[].clk = rdclk;
	rdptr_g[].clrn = (! aclr);
	rdptr_g[].d = rdptr_g1p.q[];
	rdptr_g[].ena = valid_rdreq;
	rdaclr.clock = (! rdclk);
	rdaclr.clrn = (! aclr);
	rdaclr.d[] = B"1";
	rs_brp.clock = rdclk;
	rs_brp.clrn = (! aclr);
	rs_brp.d[] = rdptr_g_gray2bin.bin[];
	rs_bwp.clock = rdclk;
	rs_bwp.clrn = (! aclr);
	rs_bwp.d[] = rs_dgwp_gray2bin.bin[];
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_brp.clock = wrclk;
	ws_brp.clrn = (! aclr);
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.clrn = (! aclr);
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g[].q;
	rdusedw_sub_result[] = rdusedw_sub_dataa[] - rdusedw_sub_datab[];
	rdusedw_sub_dataa[] = rs_bwp.q[];
	rdusedw_sub_datab[] = rs_brp.q[];
	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
	wrusedw_sub_dataa[] = ws_bwp.q[];
	wrusedw_sub_datab[] = ws_brp.q[];
	IF (rdempty_eq_comp_dataa[] == rdempty_eq_comp_datab[]) THEN
		rdempty_eq_comp_aeb_int = VCC;
	ELSE
		rdempty_eq_comp_aeb_int = GND;
	END IF;
	rdempty_eq_comp_aeb = rdempty_eq_comp_aeb_int;
	rdempty_eq_comp_dataa[] = rs_dgwp.q[];
	rdempty_eq_comp_datab[] = rdptr_g[].q;
	IF (wrfull_eq_comp_dataa[] == wrfull_eq_comp_datab[]) THEN
		wrfull_eq_comp_aeb_int = VCC;
	ELSE
		wrfull_eq_comp_aeb_int = GND;
	END IF;
	wrfull_eq_comp_aeb = wrfull_eq_comp_aeb_int;
	wrfull_eq_comp_dataa[] = ws_dgrp.q[];
	wrfull_eq_comp_datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp_aeb;
	int_wrfull = wrfull_eq_comp_aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[9..9] $ wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]);
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.q));
	rdempty = int_rdempty;
	rdusedw[] = ( rdusedw_sub_result[8..0]);
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrptr_gs[] = ( (! wrptr_gp.q[9..9]), (! wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	wrusedw[] = ( wrusedw_sub_result[8..0]);
END;
--VALID FILE