altsyncram_1l81.tdf

在altera DE2 的开发板上采集图像

--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 WIDTHAD_B=9 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=r105
--VERSION_BEGIN 8.0 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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FUNCTION altsyncram_drg1 (aclr1, address_a[8..0], address_b[8..0], addressstall_a, clock0, clock1, clocken0, clocken1, data_a[15..0], data_b[15..0], wren_a, wren_b)
RETURNS ( q_a[15..0], q_b[15..0]);

--synthesis_resources = M4K 2 
OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=r105;OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_1l81
( 
	aclr1	:	input;
	address_a[8..0]	:	input;
	address_b[8..0]	:	input;
	addressstall_b	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[15..0]	:	input;
	q_b[15..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram5 : altsyncram_drg1;

BEGIN 
	altsyncram5.aclr1 = aclr1;
	altsyncram5.address_a[] = address_b[];
	altsyncram5.address_b[] = address_a[];
	altsyncram5.addressstall_a = addressstall_b;
	altsyncram5.clock0 = clock1;
	altsyncram5.clock1 = clock0;
	altsyncram5.clocken0 = clocken1;
	altsyncram5.clocken1 = wren_a;
	altsyncram5.data_a[] = B"1111111111111111";
	altsyncram5.data_b[] = data_a[];
	altsyncram5.wren_a = B"0";
	altsyncram5.wren_b = wren_a;
	q_b[] = altsyncram5.q_a[];
END;
--VALID FILE