de2_lcm_ccd.hier_info

在altera DE2 的开发板上采集图像

wren_a => ram_block3a17.PORTAWE
wren_a => ram_block3a18.PORTAWE
wren_a => ram_block3a19.PORTAWE


|DE2_LCM_CCD|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|cntr_3rf:cntr1
clock => counter_reg_bit4a[10].CLK
clock => counter_reg_bit4a[9].CLK
clock => counter_reg_bit4a[8].CLK
clock => counter_reg_bit4a[7].CLK
clock => counter_reg_bit4a[6].CLK
clock => counter_reg_bit4a[5].CLK
clock => counter_reg_bit4a[4].CLK
clock => counter_reg_bit4a[3].CLK
clock => counter_reg_bit4a[2].CLK
clock => counter_reg_bit4a[1].CLK
clock => counter_reg_bit4a[0].CLK
q[0] <= counter_reg_bit4a[0].REGOUT
q[1] <= counter_reg_bit4a[1].REGOUT
q[2] <= counter_reg_bit4a[2].REGOUT
q[3] <= counter_reg_bit4a[3].REGOUT
q[4] <= counter_reg_bit4a[4].REGOUT
q[5] <= counter_reg_bit4a[5].REGOUT
q[6] <= counter_reg_bit4a[6].REGOUT
q[7] <= counter_reg_bit4a[7].REGOUT
q[8] <= counter_reg_bit4a[8].REGOUT
q[9] <= counter_reg_bit4a[9].REGOUT
q[10] <= counter_reg_bit4a[10].REGOUT


|DE2_LCM_CCD|SEG7_LUT_8:u5
oSEG0[0] <= SEG7_LUT:u0.port0
oSEG0[1] <= SEG7_LUT:u0.port0
oSEG0[2] <= SEG7_LUT:u0.port0
oSEG0[3] <= SEG7_LUT:u0.port0
oSEG0[4] <= SEG7_LUT:u0.port0
oSEG0[5] <= SEG7_LUT:u0.port0
oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
oSEG4[0] <= SEG7_LUT:u4.port0
oSEG4[1] <= SEG7_LUT:u4.port0
oSEG4[2] <= SEG7_LUT:u4.port0
oSEG4[3] <= SEG7_LUT:u4.port0
oSEG4[4] <= SEG7_LUT:u4.port0
oSEG4[5] <= SEG7_LUT:u4.port0
oSEG4[6] <= SEG7_LUT:u4.port0
oSEG5[0] <= SEG7_LUT:u5.port0
oSEG5[1] <= SEG7_LUT:u5.port0
oSEG5[2] <= SEG7_LUT:u5.port0
oSEG5[3] <= SEG7_LUT:u5.port0
oSEG5[4] <= SEG7_LUT:u5.port0
oSEG5[5] <= SEG7_LUT:u5.port0
oSEG5[6] <= SEG7_LUT:u5.port0
oSEG6[0] <= SEG7_LUT:u6.port0
oSEG6[1] <= SEG7_LUT:u6.port0
oSEG6[2] <= SEG7_LUT:u6.port0
oSEG6[3] <= SEG7_LUT:u6.port0
oSEG6[4] <= SEG7_LUT:u6.port0
oSEG6[5] <= SEG7_LUT:u6.port0
oSEG6[6] <= SEG7_LUT:u6.port0
oSEG7[0] <= SEG7_LUT:u7.port0
oSEG7[1] <= SEG7_LUT:u7.port0
oSEG7[2] <= SEG7_LUT:u7.port0
oSEG7[3] <= SEG7_LUT:u7.port0
oSEG7[4] <= SEG7_LUT:u7.port0
oSEG7[5] <= SEG7_LUT:u7.port0
oSEG7[6] <= SEG7_LUT:u7.port0
iDIG[0] => iDIG[0]~31.IN1
iDIG[1] => iDIG[1]~30.IN1
iDIG[2] => iDIG[2]~29.IN1
iDIG[3] => iDIG[3]~28.IN1
iDIG[4] => iDIG[4]~27.IN1
iDIG[5] => iDIG[5]~26.IN1
iDIG[6] => iDIG[6]~25.IN1
iDIG[7] => iDIG[7]~24.IN1
iDIG[8] => iDIG[8]~23.IN1
iDIG[9] => iDIG[9]~22.IN1
iDIG[10] => iDIG[10]~21.IN1
iDIG[11] => iDIG[11]~20.IN1
iDIG[12] => iDIG[12]~19.IN1
iDIG[13] => iDIG[13]~18.IN1
iDIG[14] => iDIG[14]~17.IN1
iDIG[15] => iDIG[15]~16.IN1
iDIG[16] => iDIG[16]~15.IN1
iDIG[17] => iDIG[17]~14.IN1
iDIG[18] => iDIG[18]~13.IN1
iDIG[19] => iDIG[19]~12.IN1
iDIG[20] => iDIG[20]~11.IN1
iDIG[21] => iDIG[21]~10.IN1
iDIG[22] => iDIG[22]~9.IN1
iDIG[23] => iDIG[23]~8.IN1
iDIG[24] => iDIG[24]~7.IN1
iDIG[25] => iDIG[25]~6.IN1
iDIG[26] => iDIG[26]~5.IN1
iDIG[27] => iDIG[27]~4.IN1
iDIG[28] => iDIG[28]~3.IN1
iDIG[29] => iDIG[29]~2.IN1
iDIG[30] => iDIG[30]~1.IN1
iDIG[31] => iDIG[31]~0.IN1


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u0
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|SEG7_LUT_8:u5|SEG7_LUT:u7
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCM_CCD|Sdram_Control_4Port:u6
REF_CLK => REF_CLK~0.IN1
RESET_N => RESET_N~0.IN3
WR1_DATA[0] => WR1_DATA[0]~15.IN1
WR1_DATA[1] => WR1_DATA[1]~14.IN1
WR1_DATA[2] => WR1_DATA[2]~13.IN1
WR1_DATA[3] => WR1_DATA[3]~12.IN1
WR1_DATA[4] => WR1_DATA[4]~11.IN1
WR1_DATA[5] => WR1_DATA[5]~10.IN1
WR1_DATA[6] => WR1_DATA[6]~9.IN1
WR1_DATA[7] => WR1_DATA[7]~8.IN1
WR1_DATA[8] => WR1_DATA[8]~7.IN1
WR1_DATA[9] => WR1_DATA[9]~6.IN1
WR1_DATA[10] => WR1_DATA[10]~5.IN1
WR1_DATA[11] => WR1_DATA[11]~4.IN1
WR1_DATA[12] => WR1_DATA[12]~3.IN1
WR1_DATA[13] => WR1_DATA[13]~2.IN1
WR1_DATA[14] => WR1_DATA[14]~1.IN1
WR1_DATA[15] => WR1_DATA[15]~0.IN1
WR1 => WR1~0.IN1
WR1_ADDR[0] => rWR1_ADDR~68.DATAB
WR1_ADDR[0] => rWR1_ADDR~22.DATAA
WR1_ADDR[1] => rWR1_ADDR~67.DATAB
WR1_ADDR[1] => rWR1_ADDR~21.DATAA
WR1_ADDR[2] => rWR1_ADDR~66.DATAB
WR1_ADDR[2] => rWR1_ADDR~20.DATAA
WR1_ADDR[3] => rWR1_ADDR~65.DATAB
WR1_ADDR[3] => rWR1_ADDR~19.DATAA
WR1_ADDR[4] => rWR1_ADDR~64.DATAB
WR1_ADDR[4] => rWR1_ADDR~18.DATAA
WR1_ADDR[5] => rWR1_ADDR~63.DATAB
WR1_ADDR[5] => rWR1_ADDR~17.DATAA
WR1_ADDR[6] => rWR1_ADDR~62.DATAB
WR1_ADDR[6] => rWR1_ADDR~16.DATAA
WR1_ADDR[7] => rWR1_ADDR~61.DATAB
WR1_ADDR[7] => rWR1_ADDR~15.DATAA
WR1_ADDR[8] => rWR1_ADDR~60.DATAB
WR1_ADDR[8] => rWR1_ADDR~14.DATAA
WR1_ADDR[9] => rWR1_ADDR~59.DATAB
WR1_ADDR[9] => rWR1_ADDR~13.DATAA
WR1_ADDR[10] => rWR1_ADDR~58.DATAB
WR1_ADDR[10] => rWR1_ADDR~12.DATAA
WR1_ADDR[11] => rWR1_ADDR~57.DATAB
WR1_ADDR[11] => rWR1_ADDR~11.DATAA
WR1_ADDR[12] => rWR1_ADDR~56.DATAB
WR1_ADDR[12] => rWR1_ADDR~10.DATAA
WR1_ADDR[13] => rWR1_ADDR~55.DATAB
WR1_ADDR[13] => rWR1_ADDR~9.DATAA
WR1_ADDR[14] => rWR1_ADDR~54.DATAB
WR1_ADDR[14] => rWR1_ADDR~8.DATAA
WR1_ADDR[15] => rWR1_ADDR~53.DATAB
WR1_ADDR[15] => rWR1_ADDR~7.DATAA
WR1_ADDR[16] => rWR1_ADDR~52.DATAB
WR1_ADDR[16] => rWR1_ADDR~6.DATAA
WR1_ADDR[17] => rWR1_ADDR~51.DATAB
WR1_ADDR[17] => rWR1_ADDR~5.DATAA
WR1_ADDR[18] => rWR1_ADDR~50.DATAB
WR1_ADDR[18] => rWR1_ADDR~4.DATAA
WR1_ADDR[19] => rWR1_ADDR~49.DATAB
WR1_ADDR[19] => rWR1_ADDR~3.DATAA
WR1_ADDR[20] => rWR1_ADDR~48.DATAB
WR1_ADDR[20] => rWR1_ADDR~2.DATAA
WR1_ADDR[21] => rWR1_ADDR~47.DATAB
WR1_ADDR[21] => rWR1_ADDR~1.DATAA
WR1_ADDR[22] => rWR1_ADDR~46.DATAB
WR1_ADDR[22] => rWR1_ADDR~0.DATAA
WR1_MAX_ADDR[0] => ~NO_FANOUT~
WR1_MAX_ADDR[1] => ~NO_FANOUT~
WR1_MAX_ADDR[2] => ~NO_FANOUT~
WR1_MAX_ADDR[3] => ~NO_FANOUT~
WR1_MAX_ADDR[4] => ~NO_FANOUT~
WR1_MAX_ADDR[5] => ~NO_FANOUT~
WR1_MAX_ADDR[6] => ~NO_FANOUT~
WR1_MAX_ADDR[7] => ~NO_FANOUT~
WR1_MAX_ADDR[8] => ~NO_FANOUT~
WR1_MAX_ADDR[9] => ~NO_FANOUT~
WR1_MAX_ADDR[10] => ~NO_FANOUT~
WR1_MAX_ADDR[11] => ~NO_FANOUT~
WR1_MAX_ADDR[12] => ~NO_FANOUT~
WR1_MAX_ADDR[13] => ~NO_FANOUT~
WR1_MAX_ADDR[14] => ~NO_FANOUT~
WR1_MAX_ADDR[15] => ~NO_FANOUT~
WR1_MAX_ADDR[16] => ~NO_FANOUT~
WR1_MAX_ADDR[17] => ~NO_FANOUT~
WR1_MAX_ADDR[18] => ~NO_FANOUT~
WR1_MAX_ADDR[19] => ~NO_FANOUT~
WR1_MAX_ADDR[20] => ~NO_FANOUT~
WR1_MAX_ADDR[21] => ~NO_FANOUT~
WR1_MAX_ADDR[22] => ~NO_FANOUT~
WR1_LENGTH[0] => rWR1_LENGTH[0].DATAIN
WR1_LENGTH[1] => rWR1_LENGTH[1].DATAIN
WR1_LENGTH[2] => rWR1_LENGTH[2].DATAIN
WR1_LENGTH[3] => rWR1_LENGTH[3].DATAIN
WR1_LENGTH[4] => rWR1_LENGTH[4].DATAIN
WR1_LENGTH[5] => rWR1_LENGTH[5].DATAIN
WR1_LENGTH[6] => rWR1_LENGTH[6].DATAIN
WR1_LENGTH[7] => rWR1_LENGTH[7].DATAIN
WR1_LENGTH[8] => rWR1_LENGTH[8].DATAIN
WR1_LOAD => WR1_LOAD~0.IN1
WR1_CLK => WR1_CLK~0.IN1
WR1_FULL <= Sdram_FIFO:write_fifo1.wrfull
WR1_USE[0] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[1] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[2] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[3] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[4] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[5] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[6] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[7] <= Sdram_FIFO:write_fifo1.wrusedw
WR1_USE[8] <= Sdram_FIFO:write_fifo1.wrusedw
WR2_DATA[0] => WR2_DATA[0]~15.IN1
WR2_DATA[1] => WR2_DATA[1]~14.IN1
WR2_DATA[2] => WR2_DATA[2]~13.IN1
WR2_DATA[3] => WR2_DATA[3]~12.IN1
WR2_DATA[4] => WR2_DATA[4]~11.IN1
WR2_DATA[5] => WR2_DATA[5]~10.IN1
WR2_DATA[6] => WR2_DATA[6]~9.IN1
WR2_DATA[7] => WR2_DATA[7]~8.IN1
WR2_DATA[8] => WR2_DATA[8]~7.IN1
WR2_DATA[9] => WR2_DATA[9]~6.IN1
WR2_DATA[10] => WR2_DATA[10]~5.IN1
WR2_DATA[11] => WR2_DATA[11]~4.IN1
WR2_DATA[12] => WR2_DATA[12]~3.IN1
WR2_DATA[13] => WR2_DATA[13]~2.IN1
WR2_DATA[14] => WR2_DATA[14]~1.IN1
WR2_DATA[15] => WR2_DATA[15]~0.IN1
WR2 => WR2~0.IN1
WR2_ADDR[0] => rWR2_ADDR~68.DATAB
WR2_ADDR[0] => rWR2_ADDR~22.DATAA
WR2_ADDR[1] => rWR2_ADDR~67.DATAB
WR2_ADDR[1] => rWR2_ADDR~21.DATAA
WR2_ADDR[2] => rWR2_ADDR~66.DATAB
WR2_ADDR[2] => rWR2_ADDR~20.DATAA
WR2_ADDR[3] => rWR2_ADDR~65.DATAB
WR2_ADDR[3] => rWR2_ADDR~19.DATAA
WR2_ADDR[4] => rWR2_ADDR~64.DATAB
WR2_ADDR[4] => rWR2_ADDR~18.DATAA
WR2_ADDR[5] => rWR2_ADDR~63.DATAB
WR2_ADDR[5] => rWR2_ADDR~17.DATAA
WR2_ADDR[6] => rWR2_ADDR~62.DATAB
WR2_ADDR[6] => rW