de2_lcm_ccd.hier_info

在altera DE2 的开发板上采集图像

address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[8] => ram_block3a8.PORTAADDR8
address_a[8] => ram_block3a9.PORTAADDR8
address_a[8] => ram_block3a10.PORTAADDR8
address_a[8] => ram_block3a11.PORTAADDR8
address_a[8] => ram_block3a12.PORTAADDR8
address_a[8] => ram_block3a13.PORTAADDR8
address_a[8] => ram_block3a14.PORTAADDR8
address_a[8] => ram_block3a15.PORTAADDR8
address_a[8] => ram_block3a16.PORTAADDR8
address_a[8] => ram_block3a17.PORTAADDR8
address_a[8] => ram_block3a18.PORTAADDR8
address_a[8] => ram_block3a19.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_a[9] => ram_block3a8.PORTAADDR9
address_a[9] => ram_block3a9.PORTAADDR9
address_a[9] => ram_block3a10.PORTAADDR9
address_a[9] => ram_block3a11.PORTAADDR9
address_a[9] => ram_block3a12.PORTAADDR9
address_a[9] => ram_block3a13.PORTAADDR9
address_a[9] => ram_block3a14.PORTAADDR9
address_a[9] => ram_block3a15.PORTAADDR9
address_a[9] => ram_block3a16.PORTAADDR9
address_a[9] => ram_block3a17.PORTAADDR9
address_a[9] => ram_block3a18.PORTAADDR9
address_a[9] => ram_block3a19.PORTAADDR9
address_a[10] => ram_block3a0.PORTAADDR10
address_a[10] => ram_block3a1.PORTAADDR10
address_a[10] => ram_block3a2.PORTAADDR10
address_a[10] => ram_block3a3.PORTAADDR10
address_a[10] => ram_block3a4.PORTAADDR10
address_a[10] => ram_block3a5.PORTAADDR10
address_a[10] => ram_block3a6.PORTAADDR10
address_a[10] => ram_block3a7.PORTAADDR10
address_a[10] => ram_block3a8.PORTAADDR10
address_a[10] => ram_block3a9.PORTAADDR10
address_a[10] => ram_block3a10.PORTAADDR10
address_a[10] => ram_block3a11.PORTAADDR10
address_a[10] => ram_block3a12.PORTAADDR10
address_a[10] => ram_block3a13.PORTAADDR10
address_a[10] => ram_block3a14.PORTAADDR10
address_a[10] => ram_block3a15.PORTAADDR10
address_a[10] => ram_block3a16.PORTAADDR10
address_a[10] => ram_block3a17.PORTAADDR10
address_a[10] => ram_block3a18.PORTAADDR10
address_a[10] => ram_block3a19.PORTAADDR10
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[0] => ram_block3a10.PORTBADDR
address_b[0] => ram_block3a11.PORTBADDR
address_b[0] => ram_block3a12.PORTBADDR
address_b[0] => ram_block3a13.PORTBADDR
address_b[0] => ram_block3a14.PORTBADDR
address_b[0] => ram_block3a15.PORTBADDR
address_b[0] => ram_block3a16.PORTBADDR
address_b[0] => ram_block3a17.PORTBADDR
address_b[0] => ram_block3a18.PORTBADDR
address_b[0] => ram_block3a19.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[1] => ram_block3a10.PORTBADDR1
address_b[1] => ram_block3a11.PORTBADDR1
address_b[1] => ram_block3a12.PORTBADDR1
address_b[1] => ram_block3a13.PORTBADDR1
address_b[1] => ram_block3a14.PORTBADDR1
address_b[1] => ram_block3a15.PORTBADDR1
address_b[1] => ram_block3a16.PORTBADDR1
address_b[1] => ram_block3a17.PORTBADDR1
address_b[1] => ram_block3a18.PORTBADDR1
address_b[1] => ram_block3a19.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[2] => ram_block3a10.PORTBADDR2
address_b[2] => ram_block3a11.PORTBADDR2
address_b[2] => ram_block3a12.PORTBADDR2
address_b[2] => ram_block3a13.PORTBADDR2
address_b[2] => ram_block3a14.PORTBADDR2
address_b[2] => ram_block3a15.PORTBADDR2
address_b[2] => ram_block3a16.PORTBADDR2
address_b[2] => ram_block3a17.PORTBADDR2
address_b[2] => ram_block3a18.PORTBADDR2
address_b[2] => ram_block3a19.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[3] => ram_block3a10.PORTBADDR3
address_b[3] => ram_block3a11.PORTBADDR3
address_b[3] => ram_block3a12.PORTBADDR3
address_b[3] => ram_block3a13.PORTBADDR3
address_b[3] => ram_block3a14.PORTBADDR3
address_b[3] => ram_block3a15.PORTBADDR3
address_b[3] => ram_block3a16.PORTBADDR3
address_b[3] => ram_block3a17.PORTBADDR3
address_b[3] => ram_block3a18.PORTBADDR3
address_b[3] => ram_block3a19.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[4] => ram_block3a10.PORTBADDR4
address_b[4] => ram_block3a11.PORTBADDR4
address_b[4] => ram_block3a12.PORTBADDR4
address_b[4] => ram_block3a13.PORTBADDR4
address_b[4] => ram_block3a14.PORTBADDR4
address_b[4] => ram_block3a15.PORTBADDR4
address_b[4] => ram_block3a16.PORTBADDR4
address_b[4] => ram_block3a17.PORTBADDR4
address_b[4] => ram_block3a18.PORTBADDR4
address_b[4] => ram_block3a19.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[5] => ram_block3a10.PORTBADDR5
address_b[5] => ram_block3a11.PORTBADDR5
address_b[5] => ram_block3a12.PORTBADDR5
address_b[5] => ram_block3a13.PORTBADDR5
address_b[5] => ram_block3a14.PORTBADDR5
address_b[5] => ram_block3a15.PORTBADDR5
address_b[5] => ram_block3a16.PORTBADDR5
address_b[5] => ram_block3a17.PORTBADDR5
address_b[5] => ram_block3a18.PORTBADDR5
address_b[5] => ram_block3a19.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[6] => ram_block3a8.PORTBADDR6
address_b[6] => ram_block3a9.PORTBADDR6
address_b[6] => ram_block3a10.PORTBADDR6
address_b[6] => ram_block3a11.PORTBADDR6
address_b[6] => ram_block3a12.PORTBADDR6
address_b[6] => ram_block3a13.PORTBADDR6
address_b[6] => ram_block3a14.PORTBADDR6
address_b[6] => ram_block3a15.PORTBADDR6
address_b[6] => ram_block3a16.PORTBADDR6
address_b[6] => ram_block3a17.PORTBADDR6
address_b[6] => ram_block3a18.PORTBADDR6
address_b[6] => ram_block3a19.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[7] => ram_block3a8.PORTBADDR7
address_b[7] => ram_block3a9.PORTBADDR7
address_b[7] => ram_block3a10.PORTBADDR7
address_b[7] => ram_block3a11.PORTBADDR7
address_b[7] => ram_block3a12.PORTBADDR7
address_b[7] => ram_block3a13.PORTBADDR7
address_b[7] => ram_block3a14.PORTBADDR7
address_b[7] => ram_block3a15.PORTBADDR7
address_b[7] => ram_block3a16.PORTBADDR7
address_b[7] => ram_block3a17.PORTBADDR7
address_b[7] => ram_block3a18.PORTBADDR7
address_b[7] => ram_block3a19.PORTBADDR7
address_b[8] => ram_block3a0.PORTBADDR8
address_b[8] => ram_block3a1.PORTBADDR8
address_b[8] => ram_block3a2.PORTBADDR8
address_b[8] => ram_block3a3.PORTBADDR8
address_b[8] => ram_block3a4.PORTBADDR8
address_b[8] => ram_block3a5.PORTBADDR8
address_b[8] => ram_block3a6.PORTBADDR8
address_b[8] => ram_block3a7.PORTBADDR8
address_b[8] => ram_block3a8.PORTBADDR8
address_b[8] => ram_block3a9.PORTBADDR8
address_b[8] => ram_block3a10.PORTBADDR8
address_b[8] => ram_block3a11.PORTBADDR8
address_b[8] => ram_block3a12.PORTBADDR8
address_b[8] => ram_block3a13.PORTBADDR8
address_b[8] => ram_block3a14.PORTBADDR8
address_b[8] => ram_block3a15.PORTBADDR8
address_b[8] => ram_block3a16.PORTBADDR8
address_b[8] => ram_block3a17.PORTBADDR8
address_b[8] => ram_block3a18.PORTBADDR8
address_b[8] => ram_block3a19.PORTBADDR8
address_b[9] => ram_block3a0.PORTBADDR9
address_b[9] => ram_block3a1.PORTBADDR9
address_b[9] => ram_block3a2.PORTBADDR9
address_b[9] => ram_block3a3.PORTBADDR9
address_b[9] => ram_block3a4.PORTBADDR9
address_b[9] => ram_block3a5.PORTBADDR9
address_b[9] => ram_block3a6.PORTBADDR9
address_b[9] => ram_block3a7.PORTBADDR9
address_b[9] => ram_block3a8.PORTBADDR9
address_b[9] => ram_block3a9.PORTBADDR9
address_b[9] => ram_block3a10.PORTBADDR9
address_b[9] => ram_block3a11.PORTBADDR9
address_b[9] => ram_block3a12.PORTBADDR9
address_b[9] => ram_block3a13.PORTBADDR9
address_b[9] => ram_block3a14.PORTBADDR9
address_b[9] => ram_block3a15.PORTBADDR9
address_b[9] => ram_block3a16.PORTBADDR9
address_b[9] => ram_block3a17.PORTBADDR9
address_b[9] => ram_block3a18.PORTBADDR9
address_b[9] => ram_block3a19.PORTBADDR9
address_b[10] => ram_block3a0.PORTBADDR10
address_b[10] => ram_block3a1.PORTBADDR10
address_b[10] => ram_block3a2.PORTBADDR10
address_b[10] => ram_block3a3.PORTBADDR10
address_b[10] => ram_block3a4.PORTBADDR10
address_b[10] => ram_block3a5.PORTBADDR10
address_b[10] => ram_block3a6.PORTBADDR10
address_b[10] => ram_block3a7.PORTBADDR10
address_b[10] => ram_block3a8.PORTBADDR10
address_b[10] => ram_block3a9.PORTBADDR10
address_b[10] => ram_block3a10.PORTBADDR10
address_b[10] => ram_block3a11.PORTBADDR10
address_b[10] => ram_block3a12.PORTBADDR10
address_b[10] => ram_block3a13.PORTBADDR10
address_b[10] => ram_block3a14.PORTBADDR10
address_b[10] => ram_block3a15.PORTBADDR10
address_b[10] => ram_block3a16.PORTBADDR10
address_b[10] => ram_block3a17.PORTBADDR10
address_b[10] => ram_block3a18.PORTBADDR10
address_b[10] => ram_block3a19.PORTBADDR10
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock0 => ram_block3a8.CLK0
clock0 => ram_block3a9.CLK0
clock0 => ram_block3a10.CLK0
clock0 => ram_block3a11.CLK0
clock0 => ram_block3a12.CLK0
clock0 => ram_block3a13.CLK0
clock0 => ram_block3a14.CLK0
clock0 => ram_block3a15.CLK0
clock0 => ram_block3a16.CLK0
clock0 => ram_block3a17.CLK0
clock0 => ram_block3a18.CLK0
clock0 => ram_block3a19.CLK0
clocken0 => ram_block3a0.ENA0
clocken0 => ram_block3a1.ENA0
clocken0 => ram_block3a2.ENA0
clocken0 => ram_block3a3.ENA0
clocken0 => ram_block3a4.ENA0
clocken0 => ram_block3a5.ENA0
clocken0 => ram_block3a6.ENA0
clocken0 => ram_block3a7.ENA0
clocken0 => ram_block3a8.ENA0
clocken0 => ram_block3a9.ENA0
clocken0 => ram_block3a10.ENA0
clocken0 => ram_block3a11.ENA0
clocken0 => ram_block3a12.ENA0
clocken0 => ram_block3a13.ENA0
clocken0 => ram_block3a14.ENA0
clocken0 => ram_block3a15.ENA0
clocken0 => ram_block3a16.ENA0
clocken0 => ram_block3a17.ENA0
clocken0 => ram_block3a18.ENA0
clocken0 => ram_block3a19.ENA0
data_a[0] => ram_block3a0.PORTADATAIN
data_a[1] => ram_block3a1.PORTADATAIN
data_a[2] => ram_block3a2.PORTADATAIN
data_a[3] => ram_block3a3.PORTADATAIN
data_a[4] => ram_block3a4.PORTADATAIN
data_a[5] => ram_block3a5.PORTADATAIN
data_a[6] => ram_block3a6.PORTADATAIN
data_a[7] => ram_block3a7.PORTADATAIN
data_a[8] => ram_block3a8.PORTADATAIN
data_a[9] => ram_block3a9.PORTADATAIN
data_a[10] => ram_block3a10.PORTADATAIN
data_a[11] => ram_block3a11.PORTADATAIN
data_a[12] => ram_block3a12.PORTADATAIN
data_a[13] => ram_block3a13.PORTADATAIN
data_a[14] => ram_block3a14.PORTADATAIN
data_a[15] => ram_block3a15.PORTADATAIN
data_a[16] => ram_block3a16.PORTADATAIN
data_a[17] => ram_block3a17.PORTADATAIN
data_a[18] => ram_block3a18.PORTADATAIN
data_a[19] => ram_block3a19.PORTADATAIN
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
q_b[8] <= ram_block3a8.PORTBDATAOUT
q_b[9] <= ram_block3a9.PORTBDATAOUT
q_b[10] <= ram_block3a10.PORTBDATAOUT
q_b[11] <= ram_block3a11.PORTBDATAOUT
q_b[12] <= ram_block3a12.PORTBDATAOUT
q_b[13] <= ram_block3a13.PORTBDATAOUT
q_b[14] <= ram_block3a14.PORTBDATAOUT
q_b[15] <= ram_block3a15.PORTBDATAOUT
q_b[16] <= ram_block3a16.PORTBDATAOUT
q_b[17] <= ram_block3a17.PORTBDATAOUT
q_b[18] <= ram_block3a18.PORTBDATAOUT
q_b[19] <= ram_block3a19.PORTBDATAOUT
wren_a => ram_block3a0.PORTAWE
wren_a => ram_block3a1.PORTAWE
wren_a => ram_block3a2.PORTAWE
wren_a => ram_block3a3.PORTAWE
wren_a => ram_block3a4.PORTAWE
wren_a => ram_block3a5.PORTAWE
wren_a => ram_block3a6.PORTAWE
wren_a => ram_block3a7.PORTAWE
wren_a => ram_block3a8.PORTAWE
wren_a => ram_block3a9.PORTAWE
wren_a => ram_block3a10.PORTAWE
wren_a => ram_block3a11.PORTAWE
wren_a => ram_block3a12.PORTAWE
wren_a => ram_block3a13.PORTAWE
wren_a => ram_block3a14.PORTAWE
wren_a => ram_block3a15.PORTAWE
wren_a => ram_block3a16.PORTAWE