de2_lcm_ccd.hier_info

在altera DE2 的开发板上采集图像

iY_Cont[0] => Equal1.IN1
iY_Cont[0] => Equal2.IN1
iY_Cont[0] => Equal3.IN0
iY_Cont[1] => ~NO_FANOUT~
iY_Cont[2] => ~NO_FANOUT~
iY_Cont[3] => ~NO_FANOUT~
iY_Cont[4] => ~NO_FANOUT~
iY_Cont[5] => ~NO_FANOUT~
iY_Cont[6] => ~NO_FANOUT~
iY_Cont[7] => ~NO_FANOUT~
iY_Cont[8] => ~NO_FANOUT~
iY_Cont[9] => ~NO_FANOUT~
iY_Cont[10] => ~NO_FANOUT~
iDATA[0] => iDATA[0]~9.IN1
iDATA[1] => iDATA[1]~8.IN1
iDATA[2] => iDATA[2]~7.IN1
iDATA[3] => iDATA[3]~6.IN1
iDATA[4] => iDATA[4]~5.IN1
iDATA[5] => iDATA[5]~4.IN1
iDATA[6] => iDATA[6]~3.IN1
iDATA[7] => iDATA[7]~2.IN1
iDATA[8] => iDATA[8]~1.IN1
iDATA[9] => iDATA[9]~0.IN1
iDVAL => iDVAL~0.IN1
iCLK => iCLK~0.IN1
iRST => mCCD_R[9].ACLR
iRST => mCCD_R[8].ACLR
iRST => mCCD_R[7].ACLR
iRST => mCCD_R[6].ACLR
iRST => mCCD_R[5].ACLR
iRST => mCCD_R[4].ACLR
iRST => mCCD_R[3].ACLR
iRST => mCCD_R[2].ACLR
iRST => mCCD_R[1].ACLR
iRST => mCCD_R[0].ACLR
iRST => mCCD_G[10].ACLR
iRST => mCCD_G[9].ACLR
iRST => mCCD_G[8].ACLR
iRST => mCCD_G[7].ACLR
iRST => mCCD_G[6].ACLR
iRST => mCCD_G[5].ACLR
iRST => mCCD_G[4].ACLR
iRST => mCCD_G[3].ACLR
iRST => mCCD_G[2].ACLR
iRST => mCCD_G[1].ACLR
iRST => mCCD_B[9].ACLR
iRST => mCCD_B[8].ACLR
iRST => mCCD_B[7].ACLR
iRST => mCCD_B[6].ACLR
iRST => mCCD_B[5].ACLR
iRST => mCCD_B[4].ACLR
iRST => mCCD_B[3].ACLR
iRST => mCCD_B[2].ACLR
iRST => mCCD_B[1].ACLR
iRST => mCCD_B[0].ACLR
iRST => mDATAd_0[9].ACLR
iRST => mDATAd_0[8].ACLR
iRST => mDATAd_0[7].ACLR
iRST => mDATAd_0[6].ACLR
iRST => mDATAd_0[5].ACLR
iRST => mDATAd_0[4].ACLR
iRST => mDATAd_0[3].ACLR
iRST => mDATAd_0[2].ACLR
iRST => mDATAd_0[1].ACLR
iRST => mDATAd_0[0].ACLR
iRST => mDATAd_1[9].ACLR
iRST => mDATAd_1[8].ACLR
iRST => mDATAd_1[7].ACLR
iRST => mDATAd_1[6].ACLR
iRST => mDATAd_1[5].ACLR
iRST => mDATAd_1[4].ACLR
iRST => mDATAd_1[3].ACLR
iRST => mDATAd_1[2].ACLR
iRST => mDATAd_1[1].ACLR
iRST => mDATAd_1[0].ACLR
iRST => mDVAL.ACLR


|DE2_LCM_CCD|RAW2RGB:u4|Line_Buffer:u0
clken => clken~0.IN1
clock => clock~0.IN1
shiftin[0] => shiftin[0]~9.IN1
shiftin[1] => shiftin[1]~8.IN1
shiftin[2] => shiftin[2]~7.IN1
shiftin[3] => shiftin[3]~6.IN1
shiftin[4] => shiftin[4]~5.IN1
shiftin[5] => shiftin[5]~4.IN1
shiftin[6] => shiftin[6]~3.IN1
shiftin[7] => shiftin[7]~2.IN1
shiftin[8] => shiftin[8]~1.IN1
shiftin[9] => shiftin[9]~0.IN1
shiftout[0] <= altshift_taps:altshift_taps_component.shiftout
shiftout[1] <= altshift_taps:altshift_taps_component.shiftout
shiftout[2] <= altshift_taps:altshift_taps_component.shiftout
shiftout[3] <= altshift_taps:altshift_taps_component.shiftout
shiftout[4] <= altshift_taps:altshift_taps_component.shiftout
shiftout[5] <= altshift_taps:altshift_taps_component.shiftout
shiftout[6] <= altshift_taps:altshift_taps_component.shiftout
shiftout[7] <= altshift_taps:altshift_taps_component.shiftout
shiftout[8] <= altshift_taps:altshift_taps_component.shiftout
shiftout[9] <= altshift_taps:altshift_taps_component.shiftout
taps0x[0] <= altshift_taps:altshift_taps_component.taps
taps0x[1] <= altshift_taps:altshift_taps_component.taps
taps0x[2] <= altshift_taps:altshift_taps_component.taps
taps0x[3] <= altshift_taps:altshift_taps_component.taps
taps0x[4] <= altshift_taps:altshift_taps_component.taps
taps0x[5] <= altshift_taps:altshift_taps_component.taps
taps0x[6] <= altshift_taps:altshift_taps_component.taps
taps0x[7] <= altshift_taps:altshift_taps_component.taps
taps0x[8] <= altshift_taps:altshift_taps_component.taps
taps0x[9] <= altshift_taps:altshift_taps_component.taps
taps1x[0] <= altshift_taps:altshift_taps_component.taps
taps1x[1] <= altshift_taps:altshift_taps_component.taps
taps1x[2] <= altshift_taps:altshift_taps_component.taps
taps1x[3] <= altshift_taps:altshift_taps_component.taps
taps1x[4] <= altshift_taps:altshift_taps_component.taps
taps1x[5] <= altshift_taps:altshift_taps_component.taps
taps1x[6] <= altshift_taps:altshift_taps_component.taps
taps1x[7] <= altshift_taps:altshift_taps_component.taps
taps1x[8] <= altshift_taps:altshift_taps_component.taps
taps1x[9] <= altshift_taps:altshift_taps_component.taps


|DE2_LCM_CCD|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
shiftin[0] => shift_taps_gkn:auto_generated.shiftin[0]
shiftin[1] => shift_taps_gkn:auto_generated.shiftin[1]
shiftin[2] => shift_taps_gkn:auto_generated.shiftin[2]
shiftin[3] => shift_taps_gkn:auto_generated.shiftin[3]
shiftin[4] => shift_taps_gkn:auto_generated.shiftin[4]
shiftin[5] => shift_taps_gkn:auto_generated.shiftin[5]
shiftin[6] => shift_taps_gkn:auto_generated.shiftin[6]
shiftin[7] => shift_taps_gkn:auto_generated.shiftin[7]
shiftin[8] => shift_taps_gkn:auto_generated.shiftin[8]
shiftin[9] => shift_taps_gkn:auto_generated.shiftin[9]
clock => shift_taps_gkn:auto_generated.clock
clken => shift_taps_gkn:auto_generated.clken
shiftout[0] <= shift_taps_gkn:auto_generated.shiftout[0]
shiftout[1] <= shift_taps_gkn:auto_generated.shiftout[1]
shiftout[2] <= shift_taps_gkn:auto_generated.shiftout[2]
shiftout[3] <= shift_taps_gkn:auto_generated.shiftout[3]
shiftout[4] <= shift_taps_gkn:auto_generated.shiftout[4]
shiftout[5] <= shift_taps_gkn:auto_generated.shiftout[5]
shiftout[6] <= shift_taps_gkn:auto_generated.shiftout[6]
shiftout[7] <= shift_taps_gkn:auto_generated.shiftout[7]
shiftout[8] <= shift_taps_gkn:auto_generated.shiftout[8]
shiftout[9] <= shift_taps_gkn:auto_generated.shiftout[9]
taps[0] <= shift_taps_gkn:auto_generated.taps[0]
taps[1] <= shift_taps_gkn:auto_generated.taps[1]
taps[2] <= shift_taps_gkn:auto_generated.taps[2]
taps[3] <= shift_taps_gkn:auto_generated.taps[3]
taps[4] <= shift_taps_gkn:auto_generated.taps[4]
taps[5] <= shift_taps_gkn:auto_generated.taps[5]
taps[6] <= shift_taps_gkn:auto_generated.taps[6]
taps[7] <= shift_taps_gkn:auto_generated.taps[7]
taps[8] <= shift_taps_gkn:auto_generated.taps[8]
taps[9] <= shift_taps_gkn:auto_generated.taps[9]
taps[10] <= shift_taps_gkn:auto_generated.taps[10]
taps[11] <= shift_taps_gkn:auto_generated.taps[11]
taps[12] <= shift_taps_gkn:auto_generated.taps[12]
taps[13] <= shift_taps_gkn:auto_generated.taps[13]
taps[14] <= shift_taps_gkn:auto_generated.taps[14]
taps[15] <= shift_taps_gkn:auto_generated.taps[15]
taps[16] <= shift_taps_gkn:auto_generated.taps[16]
taps[17] <= shift_taps_gkn:auto_generated.taps[17]
taps[18] <= shift_taps_gkn:auto_generated.taps[18]
taps[19] <= shift_taps_gkn:auto_generated.taps[19]
aclr => ~NO_FANOUT~


|DE2_LCM_CCD|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated
clken => altsyncram_4m81:altsyncram2.clocken0
clken => cntr_3rf:cntr1.clk_en
clock => altsyncram_4m81:altsyncram2.clock0
clock => cntr_3rf:cntr1.clock
shiftin[0] => altsyncram_4m81:altsyncram2.data_a[0]
shiftin[1] => altsyncram_4m81:altsyncram2.data_a[1]
shiftin[2] => altsyncram_4m81:altsyncram2.data_a[2]
shiftin[3] => altsyncram_4m81:altsyncram2.data_a[3]
shiftin[4] => altsyncram_4m81:altsyncram2.data_a[4]
shiftin[5] => altsyncram_4m81:altsyncram2.data_a[5]
shiftin[6] => altsyncram_4m81:altsyncram2.data_a[6]
shiftin[7] => altsyncram_4m81:altsyncram2.data_a[7]
shiftin[8] => altsyncram_4m81:altsyncram2.data_a[8]
shiftin[9] => altsyncram_4m81:altsyncram2.data_a[9]
shiftout[0] <= altsyncram_4m81:altsyncram2.q_b[10]
shiftout[1] <= altsyncram_4m81:altsyncram2.q_b[11]
shiftout[2] <= altsyncram_4m81:altsyncram2.q_b[12]
shiftout[3] <= altsyncram_4m81:altsyncram2.q_b[13]
shiftout[4] <= altsyncram_4m81:altsyncram2.q_b[14]
shiftout[5] <= altsyncram_4m81:altsyncram2.q_b[15]
shiftout[6] <= altsyncram_4m81:altsyncram2.q_b[16]
shiftout[7] <= altsyncram_4m81:altsyncram2.q_b[17]
shiftout[8] <= altsyncram_4m81:altsyncram2.q_b[18]
shiftout[9] <= altsyncram_4m81:altsyncram2.q_b[19]
taps[0] <= altsyncram_4m81:altsyncram2.q_b[0]
taps[1] <= altsyncram_4m81:altsyncram2.q_b[1]
taps[2] <= altsyncram_4m81:altsyncram2.q_b[2]
taps[3] <= altsyncram_4m81:altsyncram2.q_b[3]
taps[4] <= altsyncram_4m81:altsyncram2.q_b[4]
taps[5] <= altsyncram_4m81:altsyncram2.q_b[5]
taps[6] <= altsyncram_4m81:altsyncram2.q_b[6]
taps[7] <= altsyncram_4m81:altsyncram2.q_b[7]
taps[8] <= altsyncram_4m81:altsyncram2.q_b[8]
taps[9] <= altsyncram_4m81:altsyncram2.q_b[9]
taps[10] <= altsyncram_4m81:altsyncram2.q_b[10]
taps[11] <= altsyncram_4m81:altsyncram2.q_b[11]
taps[12] <= altsyncram_4m81:altsyncram2.q_b[12]
taps[13] <= altsyncram_4m81:altsyncram2.q_b[13]
taps[14] <= altsyncram_4m81:altsyncram2.q_b[14]
taps[15] <= altsyncram_4m81:altsyncram2.q_b[15]
taps[16] <= altsyncram_4m81:altsyncram2.q_b[16]
taps[17] <= altsyncram_4m81:altsyncram2.q_b[17]
taps[18] <= altsyncram_4m81:altsyncram2.q_b[18]
taps[19] <= altsyncram_4m81:altsyncram2.q_b[19]


|DE2_LCM_CCD|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_gkn:auto_generated|altsyncram_4m81:altsyncram2
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[0] => ram_block3a10.PORTAADDR
address_a[0] => ram_block3a11.PORTAADDR
address_a[0] => ram_block3a12.PORTAADDR
address_a[0] => ram_block3a13.PORTAADDR
address_a[0] => ram_block3a14.PORTAADDR
address_a[0] => ram_block3a15.PORTAADDR
address_a[0] => ram_block3a16.PORTAADDR
address_a[0] => ram_block3a17.PORTAADDR
address_a[0] => ram_block3a18.PORTAADDR
address_a[0] => ram_block3a19.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[1] => ram_block3a10.PORTAADDR1
address_a[1] => ram_block3a11.PORTAADDR1
address_a[1] => ram_block3a12.PORTAADDR1
address_a[1] => ram_block3a13.PORTAADDR1
address_a[1] => ram_block3a14.PORTAADDR1
address_a[1] => ram_block3a15.PORTAADDR1
address_a[1] => ram_block3a16.PORTAADDR1
address_a[1] => ram_block3a17.PORTAADDR1
address_a[1] => ram_block3a18.PORTAADDR1
address_a[1] => ram_block3a19.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[2] => ram_block3a10.PORTAADDR2
address_a[2] => ram_block3a11.PORTAADDR2
address_a[2] => ram_block3a12.PORTAADDR2
address_a[2] => ram_block3a13.PORTAADDR2
address_a[2] => ram_block3a14.PORTAADDR2
address_a[2] => ram_block3a15.PORTAADDR2
address_a[2] => ram_block3a16.PORTAADDR2
address_a[2] => ram_block3a17.PORTAADDR2
address_a[2] => ram_block3a18.PORTAADDR2
address_a[2] => ram_block3a19.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[3] => ram_block3a10.PORTAADDR3
address_a[3] => ram_block3a11.PORTAADDR3
address_a[3] => ram_block3a12.PORTAADDR3
address_a[3] => ram_block3a13.PORTAADDR3
address_a[3] => ram_block3a14.PORTAADDR3
address_a[3] => ram_block3a15.PORTAADDR3
address_a[3] => ram_block3a16.PORTAADDR3
address_a[3] => ram_block3a17.PORTAADDR3
address_a[3] => ram_block3a18.PORTAADDR3
address_a[3] => ram_block3a19.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[4] => ram_block3a10.PORTAADDR4
address_a[4] => ram_block3a11.PORTAADDR4
address_a[4] => ram_block3a12.PORTAADDR4
address_a[4] => ram_block3a13.PORTAADDR4
address_a[4] => ram_block3a14.PORTAADDR4
address_a[4] => ram_block3a15.PORTAADDR4
address_a[4] => ram_block3a16.PORTAADDR4
address_a[4] => ram_block3a17.PORTAADDR4
address_a[4] => ram_block3a18.PORTAADDR4
address_a[4] => ram_block3a19.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[5] => ram_block3a10.PORTAADDR5
address_a[5] => ram_block3a11.PORTAADDR5
address_a[5] => ram_block3a12.PORTAADDR5
address_a[5] => ram_block3a13.PORTAADDR5
address_a[5] => ram_block3a14.PORTAADDR5
address_a[5] => ram_block3a15.PORTAADDR5
address_a[5] => ram_block3a16.PORTAADDR5
address_a[5] => ram_block3a17.PORTAADDR5
address_a[5] => ram_block3a18.PORTAADDR5
address_a[5] => ram_block3a19.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[6] => ram_block3a10.PORTAADDR6
address_a[6] => ram_block3a11.PORTAADDR6
address_a[6] => ram_block3a12.PORTAADDR6
address_a[6] => ram_block3a13.PORTAADDR6
address_a[6] => ram_block3a14.PORTAADDR6
address_a[6] => ram_block3a15.PORTAADDR6
address_a[6] => ram_block3a16.PORTAADDR6
address_a[6] => ram_block3a17.PORTAADDR6
address_a[6] => ram_block3a18.PORTAADDR6
address_a[6] => ram_block3a19.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[7] => ram_block3a10.PORTAADDR7
address_a[7] => ram_block3a11.PORTAADDR7
address_a[7] => ram_block3a12.PORTAADDR7
address_a[7] => ram_block3a13.PORTAADDR7
address_a[7] => ram_block3a14.PORTAADDR7
address_a[7] => ram_block3a15.PORTAADDR7
address_a[7] => ram_block3a16.PORTAADDR7
address_a[7] => ram_block3a17.PORTAADDR7
address_a[7] => ram_block3a18.PORTAADDR7
address_a[7] => ram_block3a19.PORTAADDR7