📄 de2_lcm_ccd.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 register Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\] register Sdram_Control_4Port:u6\|WR_MASK\[0\] 3.323 ns " "Info: Slack time is 3.323 ns for clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" between source register \"Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\]\" and destination register \"Sdram_Control_4Port:u6\|WR_MASK\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "149.77 MHz 6.677 ns " "Info: Fmax is 149.77 MHz (period= 6.677 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.789 ns + Largest register register " "Info: + Largest register to register requirement is 9.789 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.642 ns " "Info: + Latch edge is 7.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 10.000 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 10.000 ns -2.358 ns 50 " "Info: Clock period of Source clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.003 ns + Largest " "Info: + Largest clock skew is 0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 destination 2.628 ns + Shortest register " "Info: + Shortest clock path from clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" to destination register is 2.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 418 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 418; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.628 ns Sdram_Control_4Port:u6\|WR_MASK\[0\] 3 REG LCFF_X45_Y9_N3 20 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.628 ns; Loc. = LCFF_X45_Y9_N3; Fanout = 20; REG Node = 'Sdram_Control_4Port:u6\|WR_MASK\[0\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.43 % ) " "Info: Total cell delay = 0.537 ns ( 20.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.091 ns ( 79.57 % ) " "Info: Total interconnect delay = 2.091 ns ( 79.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 source 2.625 ns - Longest register " "Info: - Longest clock path from clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" to source register is 2.625 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 418 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 418; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.537 ns) 2.625 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\] 3 REG LCFF_X35_Y8_N25 1 " "Info: 3: + IC(0.997 ns) + CELL(0.537 ns) = 2.625 ns; Loc. = LCFF_X35_Y8_N25; Fanout = 1; REG Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "db/dffpipe_kec.tdf" "" { Text "D:/DE2_LCM_CCD/db/dffpipe_kec.tdf" 32 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.46 % ) " "Info: Total cell delay = 0.537 ns ( 20.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.088 ns ( 79.54 % ) " "Info: Total interconnect delay = 2.088 ns ( 79.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} } { 0.000ns 1.091ns 0.997ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} } { 0.000ns 1.091ns 0.997ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "db/dffpipe_kec.tdf" "" { Text "D:/DE2_LCM_CCD/db/dffpipe_kec.tdf" 32 8 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} } { 0.000ns 1.091ns 0.997ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.466 ns - Longest register register " "Info: - Longest register to register delay is 6.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\] 1 REG LCFF_X35_Y8_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y8_N25; Fanout = 1; REG Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|dffpipe_kec:rs_bwp\|dffe8a\[3\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "db/dffpipe_kec.tdf" "" { Text "D:/DE2_LCM_CCD/db/dffpipe_kec.tdf" 32 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.414 ns) 1.150 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~155 2 COMB LCCOMB_X36_Y8_N12 1 " "Info: 2: + IC(0.736 ns) + CELL(0.414 ns) = 1.150 ns; Loc. = LCCOMB_X36_Y8_N12; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~155'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.309 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~157 3 COMB LCCOMB_X36_Y8_N14 1 " "Info: 3: + IC(0.000 ns) + CELL(0.159 ns) = 1.309 ns; Loc. = LCCOMB_X36_Y8_N14; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~157'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.380 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~159 4 COMB LCCOMB_X36_Y8_N16 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.380 ns; Loc. = LCCOMB_X36_Y8_N16; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~159'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.451 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~161 5 COMB LCCOMB_X36_Y8_N18 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.451 ns; Loc. = LCCOMB_X36_Y8_N18; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~161'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.522 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~163 6 COMB LCCOMB_X36_Y8_N20 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.522 ns; Loc. = LCCOMB_X36_Y8_N20; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~163'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.932 ns Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~164 7 COMB LCCOMB_X36_Y8_N22 7 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 1.932 ns; Loc. = LCCOMB_X36_Y8_N22; Fanout = 7; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_m2o1:auto_generated\|op_1~164'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.422 ns) + CELL(0.275 ns) 3.629 ns Sdram_Control_4Port:u6\|mWR~215 8 COMB LCCOMB_X45_Y9_N30 23 " "Info: 8: + IC(1.422 ns) + CELL(0.275 ns) = 3.629 ns; Loc. = LCCOMB_X45_Y9_N30; Fanout = 23; COMB Node = 'Sdram_Control_4Port:u6\|mWR~215'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 Sdram_Control_4Port:u6|mWR~215 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.275 ns) 4.680 ns Sdram_Control_4Port:u6\|mWR~217 9 COMB LCCOMB_X45_Y10_N28 17 " "Info: 9: + IC(0.776 ns) + CELL(0.275 ns) = 4.680 ns; Loc. = LCCOMB_X45_Y10_N28; Fanout = 17; COMB Node = 'Sdram_Control_4Port:u6\|mWR~217'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.051 ns" { Sdram_Control_4Port:u6|mWR~215 Sdram_Control_4Port:u6|mWR~217 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.149 ns) 5.087 ns Sdram_Control_4Port:u6\|mWR~219 10 COMB LCCOMB_X45_Y10_N8 3 " "Info: 10: + IC(0.258 ns) + CELL(0.149 ns) = 5.087 ns; Loc. = LCCOMB_X45_Y10_N8; Fanout = 3; COMB Node = 'Sdram_Control_4Port:u6\|mWR~219'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mWR~219 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.660 ns) 6.466 ns Sdram_Control_4Port:u6\|WR_MASK\[0\] 11 REG LCFF_X45_Y9_N3 20 " "Info: 11: + IC(0.719 ns) + CELL(0.660 ns) = 6.466 ns; Loc. = LCFF_X45_Y9_N3; Fanout = 20; REG Node = 'Sdram_Control_4Port:u6\|WR_MASK\[0\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.379 ns" { Sdram_Control_4Port:u6|mWR~219 Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.555 ns ( 39.51 % ) " "Info: Total cell delay = 2.555 ns ( 39.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.911 ns ( 60.49 % ) " "Info: Total interconnect delay = 3.911 ns ( 60.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.466 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 Sdram_Control_4Port:u6|mWR~215 Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mWR~219 Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.466 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 {} Sdram_Control_4Port:u6|mWR~215 {} Sdram_Control_4Port:u6|mWR~217 {} Sdram_Control_4Port:u6|mWR~219 {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 0.736ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.422ns 0.776ns 0.258ns 0.719ns } { 0.000ns 0.414ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.275ns 0.149ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.628 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 1.091ns 1.000ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} } { 0.000ns 1.091ns 0.997ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.466 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 Sdram_Control_4Port:u6|mWR~215 Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mWR~219 Sdram_Control_4Port:u6|WR_MASK[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.466 ns" { Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~155 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~157 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~159 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~161 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~163 {} Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|op_1~164 {} Sdram_Control_4Port:u6|mWR~215 {} Sdram_Control_4Port:u6|mWR~217 {} Sdram_Control_4Port:u6|mWR~219 {} Sdram_Control_4Port:u6|WR_MASK[0] {} } { 0.000ns 0.736ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.422ns 0.776ns 0.258ns 0.719ns } { 0.000ns 0.414ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.275ns 0.149ns 0.660ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk1\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register I2S_LCM_Config:u8\|mI2S_STR register I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en 7.284 ns " "Info: Slack time is 7.284 ns for clock \"CLOCK_50\" between source register \"I2S_LCM_Config:u8\|mI2S_STR\" and destination register \"I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "184.09 MHz 5.432 ns " "Info: Fmax is 184.09 MHz (period= 5.432 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.795 ns + Largest register register " "Info: + Largest register to register requirement is 9.795 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.009 ns + Largest " "Info: + Largest clock skew is 0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.280 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 6.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 7; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.787 ns) 3.691 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK 2 REG LCFF_X32_Y2_N25 3 " "Info: 2: + IC(1.905 ns) + CELL(0.787 ns) = 3.691 ns; Loc. = LCFF_X32_Y2_N25; Fanout = 3; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.692 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.000 ns) 4.712 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl 3 COMB CLKCTRL_G12 30 " "Info: 3: + IC(1.021 ns) + CELL(0.000 ns) = 4.712 ns; Loc. = CLKCTRL_G12; Fanout = 30; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.021 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 6.280 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en 4 REG LCFF_X41_Y16_N1 1 " "Info: 4: + IC(1.031 ns) + CELL(0.537 ns) = 6.280 ns; Loc. = LCFF_X41_Y16_N1; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 36.99 % ) " "Info: Total cell delay = 2.323 ns ( 36.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.957 ns ( 63.01 % ) " "Info: Total interconnect delay = 3.957 ns ( 63.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.271 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 7; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.787 ns) 3.691 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK 2 REG LCFF_X32_Y2_N25 3 " "Info: 2: + IC(1.905 ns) + CELL(0.787 ns) = 3.691 ns; Loc. = LCFF_X32_Y2_N25; Fanout = 3; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.692 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.000 ns) 4.712 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl 3 COMB CLKCTRL_G12 30 " "Info: 3: + IC(1.021 ns) + CELL(0.000 ns) = 4.712 ns; Loc. = CLKCTRL_G12; Fanout = 30; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.021 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 6.271 ns I2S_LCM_Config:u8\|mI2S_STR 4 REG LCFF_X50_Y16_N23 12 " "Info: 4: + IC(1.022 ns) + CELL(0.537 ns) = 6.271 ns; Loc. = LCFF_X50_Y16_N23; Fanout = 12; REG Node = 'I2S_LCM_Config:u8\|mI2S_STR'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 37.04 % ) " "Info: Total cell delay = 2.323 ns ( 37.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.948 ns ( 62.96 % ) " "Info: Total interconnect delay = 3.948 ns ( 62.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.271 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_STR {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.022ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.271 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_STR {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.022ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 138 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.271 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_STR {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.022ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.511 ns - Longest register register " "Info: - Longest register to register delay is 2.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2S_LCM_Config:u8\|mI2S_STR 1 REG LCFF_X50_Y16_N23 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X50_Y16_N23; Fanout = 12; REG Node = 'I2S_LCM_Config:u8\|mI2S_STR'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.332 ns) + CELL(0.420 ns) 0.752 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~0 2 COMB LCCOMB_X50_Y16_N18 2 " "Info: 2: + IC(0.332 ns) + CELL(0.420 ns) = 0.752 ns; Loc. = LCCOMB_X50_Y16_N18; Fanout = 2; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.752 ns" { I2S_LCM_Config:u8|mI2S_STR I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.660 ns) 2.511 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en 3 REG LCFF_X41_Y16_N1 1 " "Info: 3: + IC(1.099 ns) + CELL(0.660 ns) = 2.511 ns; Loc. = LCFF_X41_Y16_N1; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA~en'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.759 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.080 ns ( 43.01 % ) " "Info: Total cell delay = 1.080 ns ( 43.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.431 ns ( 56.99 % ) " "Info: Total interconnect delay = 1.431 ns ( 56.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { I2S_LCM_Config:u8|mI2S_STR I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { I2S_LCM_Config:u8|mI2S_STR {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.332ns 1.099ns } { 0.000ns 0.420ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.031ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_STR } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.271 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_STR {} } { 0.000ns 0.000ns 1.905ns 1.021ns 1.022ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { I2S_LCM_Config:u8|mI2S_STR I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { I2S_LCM_Config:u8|mI2S_STR {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~0 {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en {} } { 0.000ns 0.332ns 1.099ns } { 0.000ns 0.420ns 0.660ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
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