de2_lcm_ccd.tan.qmsg

在altera DE2 的开发板上采集图像

{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "mI2C_CTRL_CLK " "Warning: Clock Setting \"mI2C_CTRL_CLK\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "I2C_CCD_Config:u7\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_CCD_Config:u7\|mI2C_CTRL_CLK\" as buffer" {  } { { "I2C_CCD_Config.v" "" { Text "D:/DE2_LCM_CCD/I2C_CCD_Config.v" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_CCD_Config:u7\|mI2C_CTRL_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK " "Info: Detected ripple clock \"I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK\" as buffer" {  } { { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_ODD " "Info: Detected ripple clock \"CLK_ODD\" as buffer" {  } { { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 401 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_ODD" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u9\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_AV_Config:u9\|mI2C_CTRL_CLK\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "D:/DE2_LCM_CCD/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u9\|mI2C_CTRL_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 0}