de2_lcm_ccd.tan.qmsg

在altera DE2 的开发板上采集图像

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "GPIO_1\[10\] " "Info: Assuming node \"GPIO_1\[10\]\" is an undefined clock" {  } { { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 296 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "CLOCK_50 " "Warning: Clock Setting \"CLOCK_50\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0 "" 0 0}