📄 alt_synch_pipe_qdb.tdf
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--dffpipe DELAY=1 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;suppress_da_rule_internal=r105
--VERSION_BEGIN 8.0 cbx_a_gray2bin 2008:02:23:252825 cbx_a_graycounter 2008:02:23:252825 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_dcfifo 2008:04:22:277785 cbx_fifo_common 2008:02:23:252825 cbx_flex10ke 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689 VERSION_END
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION dffpipe_oe9 (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
--synthesis_resources = reg 10
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;suppress_da_rule_internal=r105";
SUBDESIGN alt_synch_pipe_qdb
(
clock : input;
clrn : input;
d[9..0] : input;
q[9..0] : output;
)
VARIABLE
dffpipe9 : dffpipe_oe9;
BEGIN
dffpipe9.clock = clock;
dffpipe9.clrn = clrn;
dffpipe9.d[] = d[];
q[] = dffpipe9.q[];
END;
--VALID FILE
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