de2_lcm_ccd.hif

在altera DE2 的开发板上采集图像

PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK6
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATAOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
c:|altera|80|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
}
# hierarchies {
Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
}
# macro_sequence

# end
# entity
control_interface
# storage
db|DE2_LCM_CCD.(17).cnf
db|DE2_LCM_CCD.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_4Port|control_interface.v
f269f46e0f3381c10fa32654c9c72f3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_4Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_4Port:u6|control_interface:control1
}
# macro_sequence
ASIZE23      ASIZE23      ASIZE23      
# end
# entity
command
# storage
db|DE2_LCM_CCD.(18).cnf
db|DE2_LCM_CCD.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_4Port|command.v
a7e807ca3959293dc31eb77e38aa3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_4Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_4Port:u6|command:command1
}
# macro_sequence
ASIZE23      ROWSIZE12COLSIZE8BANKSIZE2ROWSTART8          ROWSIZE12ROWSTART8          COLSTART0COLSIZE8COLSTART0BANKSTART20BANKSIZE2BANKSTART20ASIZE23      ASIZE23      
# end
# entity
sdr_data_path
# storage
db|DE2_LCM_CCD.(19).cnf
db|DE2_LCM_CCD.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_4Port|sdr_data_path.v
de752ab9c4558778f4e7459f1a713ee
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INIT_PER
24000
PARAMETER_SIGNED_DEC
DEF
REF_PER
1024
PARAMETER_SIGNED_DEC
DEF
SC_CL
3
PARAMETER_SIGNED_DEC
DEF
SC_RCD
3
PARAMETER_SIGNED_DEC
DEF
SC_RRD
7
PARAMETER_SIGNED_DEC
DEF
SC_PM
1
PARAMETER_SIGNED_DEC
DEF
SC_BL
1
PARAMETER_SIGNED_DEC
DEF
SDR_BL
111
PARAMETER_UNSIGNED_BIN
DEF
SDR_BT
0
PARAMETER_UNSIGNED_BIN
DEF
SDR_CL
011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
Sdram_Control_4Port|Sdram_Params.h
f275caceb2982a5c6261a9748b135245
}
# hierarchies {
Sdram_Control_4Port:u6|sdr_data_path:data_path1
}
# macro_sequence
DSIZE16      DSIZE16      DSIZE16      DSIZE16      DSIZE16      DSIZE16      
# end
# entity
Sdram_FIFO
# storage
db|DE2_LCM_CCD.(20).cnf
db|DE2_LCM_CCD.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Sdram_Control_4Port|Sdram_FIFO.v
9cc121d581969f3647cf6cb0deeed2d
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1
Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2
Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1
Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2
}
# macro_sequence

# end
# entity
dcfifo
# storage
db|DE2_LCM_CCD.(21).cnf
db|DE2_LCM_CCD.(21).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|dcfifo.tdf
9273101675de18bbedcc4ed54e5d6
6
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
WRSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
ADD_USEDW_MSB_BIT
OFF
PARAMETER_UNKNOWN
DEF
WRITE_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
dcfifo_m2o1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
aclr
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
c:|altera|80|quartus|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
c:|altera|80|quartus|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
c:|altera|80|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|80|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
c:|altera|80|quartus|libraries|megafunctions|lpm_counter.inc
7f888b135ddf66f0653c44cb18ac5
c:|altera|80|quartus|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
c:|altera|80|quartus|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
c:|altera|80|quartus|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
}
# hierarchies {
Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
}
# macro_sequence

# end
# entity
dcfifo_m2o1
# storage
db|DE2_LCM_CCD.(22).cnf
db|DE2_LCM_CCD.(22).cnf
# case_insensitive
# source_file
db|dcfifo_m2o1.tdf
7ca1c359ec472441d4f652c849f516d
6
# used_port {
wrusedw8
-1
3
wrusedw7
-1
3
wrusedw6
-1
3
wrusedw5
-1
3
wrusedw4
-1
3
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw8
-1
3
rdusedw7
-1
3
rdusedw6
-1
3
rdusedw5
-1
3
rdusedw4
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0