📄 prev_cmp_de2_lcm_ccd.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 register Reset_Delay:u2\|oRST_0 register Sdram_Control_4Port:u6\|mADDR\[22\] 3.384 ns " "Info: Slack time is 3.384 ns for clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" between source register \"Reset_Delay:u2\|oRST_0\" and destination register \"Sdram_Control_4Port:u6\|mADDR\[22\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.401 ns + Largest register register " "Info: + Largest register to register requirement is 7.401 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.642 ns + " "Info: + Setup relationship between source and destination is 7.642 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.642 ns " "Info: + Latch edge is 7.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 10.000 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.027 ns + Largest " "Info: + Largest clock skew is -0.027 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 destination 2.664 ns + Shortest register " "Info: + Shortest clock path from clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0\" to destination register is 2.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 418 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 418; COMB Node = 'Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.664 ns Sdram_Control_4Port:u6\|mADDR\[22\] 3 REG LCFF_X30_Y15_N11 1 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X30_Y15_N11; Fanout = 1; REG Node = 'Sdram_Control_4Port:u6\|mADDR\[22\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.16 % ) " "Info: Total cell delay = 0.537 ns ( 20.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.127 ns ( 79.84 % ) " "Info: Total interconnect delay = 2.127 ns ( 79.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 1.091ns 1.036ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.691 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 7; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 105 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 105; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns Reset_Delay:u2\|oRST_0 3 REG LCFF_X29_Y15_N13 11 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X29_Y15_N13; Fanout = 11; REG Node = 'Reset_Delay:u2\|oRST_0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { CLOCK_50~clkctrl Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "D:/DE2_LCM_CCD/Reset_Delay.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.691 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.691 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Reset_Delay:u2|oRST_0 {} } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 1.091ns 1.036ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.691 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.691 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Reset_Delay:u2|oRST_0 {} } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "Reset_Delay.v" "" { Text "D:/DE2_LCM_CCD/Reset_Delay.v" 4 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 1.091ns 1.036ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.691 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.691 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Reset_Delay:u2|oRST_0 {} } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.017 ns - Longest register register " "Info: - Longest register to register delay is 4.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:u2\|oRST_0 1 REG LCFF_X29_Y15_N13 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y15_N13; Fanout = 11; REG Node = 'Reset_Delay:u2\|oRST_0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "D:/DE2_LCM_CCD/Reset_Delay.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.868 ns) + CELL(0.150 ns) 1.018 ns Sdram_Control_4Port:u6\|mWR~213 2 COMB LCCOMB_X29_Y13_N6 1 " "Info: 2: + IC(0.868 ns) + CELL(0.150 ns) = 1.018 ns; Loc. = LCCOMB_X29_Y13_N6; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|mWR~213'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { Reset_Delay:u2|oRST_0 Sdram_Control_4Port:u6|mWR~213 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.438 ns) 1.724 ns Sdram_Control_4Port:u6\|mWR~214 3 COMB LCCOMB_X29_Y13_N14 1 " "Info: 3: + IC(0.268 ns) + CELL(0.438 ns) = 1.724 ns; Loc. = LCCOMB_X29_Y13_N14; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|mWR~214'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { Sdram_Control_4Port:u6|mWR~213 Sdram_Control_4Port:u6|mWR~214 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.378 ns) 2.364 ns Sdram_Control_4Port:u6\|mWR~217 4 COMB LCCOMB_X29_Y13_N18 17 " "Info: 4: + IC(0.262 ns) + CELL(0.378 ns) = 2.364 ns; Loc. = LCCOMB_X29_Y13_N18; Fanout = 17; COMB Node = 'Sdram_Control_4Port:u6\|mWR~217'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.640 ns" { Sdram_Control_4Port:u6|mWR~214 Sdram_Control_4Port:u6|mWR~217 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.660 ns) 4.017 ns Sdram_Control_4Port:u6\|mADDR\[22\] 5 REG LCFF_X30_Y15_N11 1 " "Info: 5: + IC(0.993 ns) + CELL(0.660 ns) = 4.017 ns; Loc. = LCFF_X30_Y15_N11; Fanout = 1; REG Node = 'Sdram_Control_4Port:u6\|mADDR\[22\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.653 ns" { Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 40.48 % ) " "Info: Total cell delay = 1.626 ns ( 40.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.391 ns ( 59.52 % ) " "Info: Total interconnect delay = 2.391 ns ( 59.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { Reset_Delay:u2|oRST_0 Sdram_Control_4Port:u6|mWR~213 Sdram_Control_4Port:u6|mWR~214 Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { Reset_Delay:u2|oRST_0 {} Sdram_Control_4Port:u6|mWR~213 {} Sdram_Control_4Port:u6|mWR~214 {} Sdram_Control_4Port:u6|mWR~217 {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 0.868ns 0.268ns 0.262ns 0.993ns } { 0.000ns 0.150ns 0.438ns 0.378ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.664 ns" { Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 {} Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0~clkctrl {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 1.091ns 1.036ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.691 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.691 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Reset_Delay:u2|oRST_0 {} } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { Reset_Delay:u2|oRST_0 Sdram_Control_4Port:u6|mWR~213 Sdram_Control_4Port:u6|mWR~214 Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mADDR[22] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { Reset_Delay:u2|oRST_0 {} Sdram_Control_4Port:u6|mWR~213 {} Sdram_Control_4Port:u6|mWR~214 {} Sdram_Control_4Port:u6|mWR~217 {} Sdram_Control_4Port:u6|mADDR[22] {} } { 0.000ns 0.868ns 0.268ns 0.262ns 0.993ns } { 0.000ns 0.150ns 0.438ns 0.378ns 0.660ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"Sdram_Control_4Port:u6\|Sdram_PLL:sdram_pll1\|altpll:altpll_component\|_clk1\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register I2S_LCM_Config:u8\|mI2S_DATA\[12\] register I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA 6.823 ns " "Info: Slack time is 6.823 ns for clock \"CLOCK_50\" between source register \"I2S_LCM_Config:u8\|mI2S_DATA\[12\]\" and destination register \"I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "157.38 MHz 6.354 ns " "Info: Fmax is 157.38 MHz (period= 6.354 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.786 ns + Largest register register " "Info: + Largest register to register requirement is 9.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.256 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 6.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 7; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.787 ns) 2.853 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK 2 REG LCFF_X24_Y20_N9 3 " "Info: 2: + IC(1.067 ns) + CELL(0.787 ns) = 2.853 ns; Loc. = LCFF_X24_Y20_N9; Fanout = 3; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.854 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.000 ns) 4.695 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl 3 COMB CLKCTRL_G10 30 " "Info: 3: + IC(1.842 ns) + CELL(0.000 ns) = 4.695 ns; Loc. = CLKCTRL_G10; Fanout = 30; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.842 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 6.256 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA 4 REG LCFF_X57_Y18_N17 1 " "Info: 4: + IC(1.024 ns) + CELL(0.537 ns) = 6.256 ns; Loc. = LCFF_X57_Y18_N17; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 37.13 % ) " "Info: Total cell delay = 2.323 ns ( 37.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.933 ns ( 62.87 % ) " "Info: Total interconnect delay = 3.933 ns ( 62.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.256 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 7; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_CCD.v" "" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.787 ns) 2.853 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK 2 REG LCFF_X24_Y20_N9 3 " "Info: 2: + IC(1.067 ns) + CELL(0.787 ns) = 2.853 ns; Loc. = LCFF_X24_Y20_N9; Fanout = 3; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.854 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.000 ns) 4.695 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl 3 COMB CLKCTRL_G10 30 " "Info: 3: + IC(1.842 ns) + CELL(0.000 ns) = 4.695 ns; Loc. = CLKCTRL_G10; Fanout = 30; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.842 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 6.256 ns I2S_LCM_Config:u8\|mI2S_DATA\[12\] 4 REG LCFF_X57_Y18_N13 1 " "Info: 4: + IC(1.024 ns) + CELL(0.537 ns) = 6.256 ns; Loc. = LCFF_X57_Y18_N13; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|mI2S_DATA\[12\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 37.13 % ) " "Info: Total cell delay = 2.323 ns ( 37.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.933 ns ( 62.87 % ) " "Info: Total interconnect delay = 3.933 ns ( 62.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_DATA[12] {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_DATA[12] {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 76 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 71 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_DATA[12] {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.963 ns - Longest register register " "Info: - Longest register to register delay is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2S_LCM_Config:u8\|mI2S_DATA\[12\] 1 REG LCFF_X57_Y18_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y18_N13; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|mI2S_DATA\[12\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "D:/DE2_LCM_CCD/I2S_LCM_Config.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.438 ns) 0.765 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~370 2 COMB LCCOMB_X57_Y18_N22 1 " "Info: 2: + IC(0.327 ns) + CELL(0.438 ns) = 0.765 ns; Loc. = LCCOMB_X57_Y18_N22; Fanout = 1; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~370'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.765 ns" { I2S_LCM_Config:u8|mI2S_DATA[12] I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.420 ns) 1.436 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~371 3 COMB LCCOMB_X57_Y18_N2 1 " "Info: 3: + IC(0.251 ns) + CELL(0.420 ns) = 1.436 ns; Loc. = LCCOMB_X57_Y18_N2; Fanout = 1; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~371'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.671 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.275 ns) 2.178 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~372 4 COMB LCCOMB_X57_Y18_N20 1 " "Info: 4: + IC(0.467 ns) + CELL(0.275 ns) = 2.178 ns; Loc. = LCCOMB_X57_Y18_N20; Fanout = 1; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~372'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.438 ns) 2.879 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~375 5 COMB LCCOMB_X57_Y18_N16 1 " "Info: 5: + IC(0.263 ns) + CELL(0.438 ns) = 2.879 ns; Loc. = LCCOMB_X57_Y18_N16; Fanout = 1; COMB Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|Mux0~375'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.701 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.963 ns I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA 6 REG LCFF_X57_Y18_N17 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.963 ns; Loc. = LCFF_X57_Y18_N17; Fanout = 1; REG Node = 'I2S_LCM_Config:u8\|I2S_Controller:u0\|mSDATA'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/DE2_LCM_CCD/I2S_Controller.v" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.655 ns ( 55.86 % ) " "Info: Total cell delay = 1.655 ns ( 55.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.308 ns ( 44.14 % ) " "Info: Total interconnect delay = 1.308 ns ( 44.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { I2S_LCM_Config:u8|mI2S_DATA[12] I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { I2S_LCM_Config:u8|mI2S_DATA[12] {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.327ns 0.251ns 0.467ns 0.263ns 0.000ns } { 0.000ns 0.438ns 0.420ns 0.275ns 0.438ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.256 ns" { CLOCK_50 I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u8|mI2S_DATA[12] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.256 ns" { CLOCK_50 {} CLOCK_50~combout {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK {} I2S_LCM_Config:u8|I2S_Controller:u0|mI2S_CLK~clkctrl {} I2S_LCM_Config:u8|mI2S_DATA[12] {} } { 0.000ns 0.000ns 1.067ns 1.842ns 1.024ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { I2S_LCM_Config:u8|mI2S_DATA[12] I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { I2S_LCM_Config:u8|mI2S_DATA[12] {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~370 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~371 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~372 {} I2S_LCM_Config:u8|I2S_Controller:u0|Mux0~375 {} I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA {} } { 0.000ns 0.327ns 0.251ns 0.467ns 0.263ns 0.000ns } { 0.000ns 0.438ns 0.420ns 0.275ns 0.438ns 0.084ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
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