de2_lcm_ccd.map.qmsg

在altera DE2 的开发板上采集图像

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 CCD_Capture.v(83) " "Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(83): truncated value with size 32 to match size of target (11)" {  } { { "CCD_Capture.v" "" { Text "D:/DE2_LCM_CCD/CCD_Capture.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "RAW2RGB.v 1 1 " "Warning: Using design file RAW2RGB.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Info: Found entity 1: RAW2RGB" {  } { { "RAW2RGB.v" "" { Text "D:/DE2_LCM_CCD/RAW2RGB.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB RAW2RGB:u4 " "Info: Elaborating entity \"RAW2RGB\" for hierarchy \"RAW2RGB:u4\"" {  } { { "DE2_LCM_CCD.v" "u4" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 468 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Line_Buffer.v 1 1 " "Warning: Using design file Line_Buffer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Info: Found entity 1: Line_Buffer" {  } { { "Line_Buffer.v" "" { Text "D:/DE2_LCM_CCD/Line_Buffer.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer RAW2RGB:u4\|Line_Buffer:u0 " "Info: Elaborating entity \"Line_Buffer\" for hierarchy \"RAW2RGB:u4\|Line_Buffer:u0\"" {  } { { "RAW2RGB.v" "u0" { Text "D:/DE2_LCM_CCD/RAW2RGB.v" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Info: Elaborating entity \"altshift_taps\" for hierarchy \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "Line_Buffer.v" "altshift_taps_component" { Text "D:/DE2_LCM_CCD/Line_Buffer.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Info: Elaborated megafunction instantiation \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "Line_Buffer.v" "" { Text "D:/DE2_LCM_CCD/Line_Buffer.v" 64 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Info: Instantiated megafunction \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Info: Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 2 " "Info: Parameter \"number_of_taps\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 1280 " "Info: Parameter \"tap_distance\" = \"1280\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 10 " "Info: Parameter \"width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "Line_Buffer.v" "" { Text "D:/DE2_LCM_CCD/Line_Buffer.v" 64 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_gkn.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/shift_taps_gkn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_gkn " "Info: Found entity 1: shift_taps_gkn" {  } { { "db/shift_taps_gkn.tdf" "" { Text "D:/DE2_LCM_CCD/db/shift_taps_gkn.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_gkn RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated " "Info: Elaborating entity \"shift_taps_gkn\" for hierarchy \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/80/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4m81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4m81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4m81 " "Info: Found entity 1: altsyncram_4m81" {  } { { "db/altsyncram_4m81.tdf" "" { Text "D:/DE2_LCM_CCD/db/altsyncram_4m81.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4m81 RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|altsyncram_4m81:altsyncram2 " "Info: Elaborating entity \"altsyncram_4m81\" for hierarchy \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|altsyncram_4m81:altsyncram2\"" {  } { { "db/shift_taps_gkn.tdf" "altsyncram2" { Text "D:/DE2_LCM_CCD/db/shift_taps_gkn.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_3rf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_3rf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_3rf " "Info: Found entity 1: cntr_3rf" {  } { { "db/cntr_3rf.tdf" "" { Text "D:/DE2_LCM_CCD/db/cntr_3rf.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_3rf RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|cntr_3rf:cntr1 " "Info: Elaborating entity \"cntr_3rf\" for hierarchy \"RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_gkn:auto_generated\|cntr_3rf:cntr1\"" {  } { { "db/shift_taps_gkn.tdf" "cntr1" { Text "D:/DE2_LCM_CCD/db/shift_taps_gkn.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SEG7_LUT_8.v 1 1 " "Warning: Using design file SEG7_LUT_8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Info: Found entity 1: SEG7_LUT_8" {  } { { "SEG7_LUT_8.v" "" { Text "D:/DE2_LCM_CCD/SEG7_LUT_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 SEG7_LUT_8:u5 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"SEG7_LUT_8:u5\"" {  } { { "DE2_LCM_CCD.v" "u5" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 474 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SEG7_LUT.v 1 1 " "Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "D:/DE2_LCM_CCD/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_8:u5\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT_8:u5\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "D:/DE2_LCM_CCD/SEG7_LUT_8.v" 5 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port Sdram_Control_4Port:u6 " "Info: Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"Sdram_Control_4Port:u6\"" {  } { { "DE2_LCM_CCD.v" "u6" { Text "D:/DE2_LCM_CCD/DE2_LCM_CCD.v" 521 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sdram_Control_4Port.v(368) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(368): truncated value with size 32 to match size of target (10)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 368 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(412) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(412): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 412 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(413) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(413): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 413 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(414) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(414): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 414 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(415) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(415): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 415 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(416) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(416): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 416 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(417) " "Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(417): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 417 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(406) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(406): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 406 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(406) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(406): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 406 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(406) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(406): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 406 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(406) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(406): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 406 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(406) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(406)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 406 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(406) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(406)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.