prev_cmp_de2_lcm_ccd.fit.qmsg

在altera DE2 的开发板上采集图像

{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 EC " "Extra Info: Packed 16 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "12 I/O " "Extra Info: Packed 12 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Info: Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:06 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.852 ns register register " "Info: Estimated most critical path is register to register delay of 3.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:u2\|oRST_0 1 REG LAB_X29_Y15 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y15; Fanout = 11; REG Node = 'Reset_Delay:u2\|oRST_0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "D:/DE2_LCM_CCD/Reset_Delay.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.150 ns) 1.109 ns Sdram_Control_4Port:u6\|mWR~213 2 COMB LAB_X29_Y13 1 " "Info: 2: + IC(0.959 ns) + CELL(0.150 ns) = 1.109 ns; Loc. = LAB_X29_Y13; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|mWR~213'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.109 ns" { Reset_Delay:u2|oRST_0 Sdram_Control_4Port:u6|mWR~213 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 1.674 ns Sdram_Control_4Port:u6\|mWR~214 3 COMB LAB_X29_Y13 1 " "Info: 3: + IC(0.127 ns) + CELL(0.438 ns) = 1.674 ns; Loc. = LAB_X29_Y13; Fanout = 1; COMB Node = 'Sdram_Control_4Port:u6\|mWR~214'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { Sdram_Control_4Port:u6|mWR~213 Sdram_Control_4Port:u6|mWR~214 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.398 ns) 2.199 ns Sdram_Control_4Port:u6\|mWR~217 4 COMB LAB_X29_Y13 17 " "Info: 4: + IC(0.127 ns) + CELL(0.398 ns) = 2.199 ns; Loc. = LAB_X29_Y13; Fanout = 17; COMB Node = 'Sdram_Control_4Port:u6\|mWR~217'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.525 ns" { Sdram_Control_4Port:u6|mWR~214 Sdram_Control_4Port:u6|mWR~217 } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.660 ns) 3.852 ns Sdram_Control_4Port:u6\|mADDR\[8\] 5 REG LAB_X31_Y14 1 " "Info: 5: + IC(0.993 ns) + CELL(0.660 ns) = 3.852 ns; Loc. = LAB_X31_Y14; Fanout = 1; REG Node = 'Sdram_Control_4Port:u6\|mADDR\[8\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.653 ns" { Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mADDR[8] } "NODE_NAME" } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v" 547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 42.73 % ) " "Info: Total cell delay = 1.646 ns ( 42.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.206 ns ( 57.27 % ) " "Info: Total interconnect delay = 2.206 ns ( 57.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.852 ns" { Reset_Delay:u2|oRST_0 Sdram_Control_4Port:u6|mWR~213 Sdram_Control_4Port:u6|mWR~214 Sdram_Control_4Port:u6|mWR~217 Sdram_Control_4Port:u6|mADDR[8] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}