de2_lcm_ccd.map.rpt

在altera DE2 的开发板上采集图像

; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; DSP Block Balancing                                          ; Auto               ; Auto               ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Optimization Technique                                       ; Balanced           ; Balanced           ;
; Carry Chain Length                                           ; 70                 ; 70                 ;
; Auto Carry Chains                                            ; On                 ; On                 ;
; Auto Open-Drain Pins                                         ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                ; Off                ;
; Perform gate-level register retiming                         ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax       ; On                 ; On                 ;
; Auto ROM Replacement                                         ; On                 ; On                 ;
; Auto RAM Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                              ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                ; On                 ; On                 ;
; Strict RAM Replacement                                       ; Off                ; Off                ;
; Allow Synchronous Control Signals                            ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                          ;
+-------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path          ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                       ;
+-------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/command.v                       ;
; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/control_interface.v             ;
; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/sdr_data_path.v                 ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Control_4Port.v           ;
; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_FIFO.v                    ;
; Sdram_Control_4Port/Sdram_PLL.v           ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_PLL.v                     ;
; DE2_LCM_CCD.v                             ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/DE2_LCM_CCD.v                                       ;
; I2S_Controller.v                          ; yes             ; User Verilog HDL File        ; D:/DE2_LCM_CCD/I2S_Controller.v                                    ;
; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; Other                        ; D:/DE2_LCM_CCD/Sdram_Control_4Port/Sdram_Params.h                  ;
; Reset_Delay.v                             ; yes             ; Other                        ; D:/DE2_LCM_CCD/Reset_Delay.v                                       ;
; CCD_Capture.v                             ; yes             ; Other                        ; D:/DE2_LCM_CCD/CCD_Capture.v                                       ;
; RAW2RGB.v                                 ; yes             ; Other                        ; D:/DE2_LCM_CCD/RAW2RGB.v                                           ;
; Line_Buffer.v                             ; yes             ; Other                        ; D:/DE2_LCM_CCD/Line_Buffer.v                                       ;
; altshift_taps.tdf                         ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altshift_taps.tdf     ;
; altdpram.inc                              ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altdpram.inc          ;
; lpm_counter.inc                           ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_counter.inc       ;
; lpm_compare.inc                           ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_compare.inc       ;
; lpm_constant.inc                          ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_constant.inc      ;
; db/shift_taps_gkn.tdf                     ; yes             ; Auto-Generated Megafunction  ; D:/DE2_LCM_CCD/db/shift_taps_gkn.tdf                               ;