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📄 de2_lcm_ccd.map.rpt

📁 在altera DE2 的开发板上采集图像
💻 RPT
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 75. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_brp
 76. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_oe9:ws_bwp
 77. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp
 78. Source assignments for Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|alt_synch_pipe_ud8:ws_dgrp|dffpipe_pe9:dffpipe11
 79. Source assignments for I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated
 80. Parameter Settings for User Entity Instance: RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
 81. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6
 82. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
 83. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|control_interface:control1
 84. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|command:command1
 85. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|sdr_data_path:data_path1
 86. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
 87. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
 88. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
 89. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
 90. Parameter Settings for User Entity Instance: I2C_CCD_Config:u7
 91. Parameter Settings for User Entity Instance: I2S_LCM_Config:u8
 92. Parameter Settings for User Entity Instance: I2S_LCM_Config:u8|I2S_Controller:u0
 93. Parameter Settings for User Entity Instance: I2C_AV_Config:u9
 94. Parameter Settings for User Entity Instance: SPI_Control:u11
 95. Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u9|altsyncram:Ram0_rtl_0
 96. altshift_taps Parameter Settings by Entity Instance
 97. dcfifo Parameter Settings by Entity Instance
 98. Analysis & Synthesis Messages
 99. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Jul 01 18:48:42 2008    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; DE2_LCM_CCD                              ;
; Top-level Entity Name              ; DE2_LCM_CCD                              ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 1,339                                    ;
;     Total combinational functions  ; 1,339                                    ;
;     Dedicated logic registers      ; 913                                      ;
; Total registers                    ; 913                                      ;
; Total pins                         ; 425                                      ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 42,968                                   ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 1                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP2C35F672C6       ;                    ;
; Top-level entity name                                        ; DE2_LCM_CCD        ; DE2_LCM_CCD        ;
; Family name                                                  ; Cyclone II         ; Stratix            ;
; Use smart compilation                                        ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                  ; 1                  ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;

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