de2_lcm_ccd.tan.rpt

在altera DE2 的开发板上采集图像

; 3.515 ns                                ; 154.20 MHz ( period = 6.485 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.273 ns                ;
; 3.515 ns                                ; 154.20 MHz ( period = 6.485 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.273 ns                ;
; 3.516 ns                                ; 154.23 MHz ( period = 6.484 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.272 ns                ;
; 3.520 ns                                ; 154.32 MHz ( period = 6.480 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[13]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.267 ns                ;
; 3.528 ns                                ; 154.51 MHz ( period = 6.472 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[16]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.260 ns                ;
; 3.528 ns                                ; 154.51 MHz ( period = 6.472 ns )                    ; Sdram_Control_4Port:u6|IN_REQ                                                                                                 ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.259 ns                ;
; 3.533 ns                                ; 154.63 MHz ( period = 6.467 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.255 ns                ;
; 3.536 ns                                ; 154.70 MHz ( period = 6.464 ns )                    ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                             ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[7] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.777 ns                  ; 6.241 ns                ;
; 3.544 ns                                ; 154.89 MHz ( period = 6.456 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[13]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.243 ns                ;
; 3.552 ns                                ; 155.09 MHz ( period = 6.448 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[16]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.236 ns                ;
; 3.557 ns                                ; 155.21 MHz ( period = 6.443 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.231 ns                ;
; 3.564 ns                                ; 155.38 MHz ( period = 6.436 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[13]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.223 ns                ;
; 3.565 ns                                ; 155.40 MHz ( period = 6.435 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.223 ns                ;
; 3.568 ns                                ; 155.47 MHz ( period = 6.432 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.228 ns                ;
; 3.571 ns                                ; 155.55 MHz ( period = 6.429 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.225 ns                ;
; 3.572 ns                                ; 155.57 MHz ( period = 6.428 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[16]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.216 ns                ;
; 3.577 ns                                ; 155.69 MHz ( period = 6.423 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.211 ns                ;
; 3.577 ns                                ; 155.69 MHz ( period = 6.423 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.211 ns                ;
; 3.586 ns                                ; 155.91 MHz ( period = 6.414 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.202 ns                ;
; 3.586 ns                                ; 155.91 MHz ( period = 6.414 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.202 ns                ;
; 3.586 ns                                ; 155.91 MHz ( period = 6.414 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.202 ns                ;
; 3.586 ns                                ; 155.91 MHz ( period = 6.414 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.202 ns                ;
; 3.589 ns                                ; 155.98 MHz ( period = 6.411 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.199 ns                ;
; 3.589 ns                                ; 155.98 MHz ( period = 6.411 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.199 ns                ;
; 3.589 ns                                ; 155.98 MHz ( period = 6.411 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.199 ns                ;
; 3.589 ns                                ; 155.98 MHz ( period = 6.411 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.199 ns                ;
; 3.602 ns                                ; 156.30 MHz ( period = 6.398 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[4] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.186 ns                ;
; 3.602 ns                                ; 156.30 MHz ( period = 6.398 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[4] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.186 ns                ;
; 3.602 ns                                ; 156.30 MHz ( period = 6.398 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[4] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.186 ns                ;
; 3.620 ns                                ; 156.74 MHz ( period = 6.380 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.176 ns                ;
; 3.632 ns                                ; 157.04 MHz ( period = 6.368 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.164 ns                ;
; 3.635 ns                                ; 157.11 MHz ( period = 6.365 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[13]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.152 ns                ;
; 3.638 ns                                ; 157.18 MHz ( period = 6.362 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.150 ns                ;
; 3.638 ns                                ; 157.18 MHz ( period = 6.362 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[13]