spi_control.v.bak

在altera DE2 的开发板上采集图像

module SPI_Control(RESET_N,iCLK,DO_START,DO_STOP,DO_IRQ,DATA,DO_READ,SS_N,CE,MOSI);
input RESET_N;
input iCLK;
input DO_START;
input DO_STOP;
input DO_IRQ;
input DATA;
output DO_READ;
output SS_N;
output CE;
output MOSI;


reg [39:0] shift_regs_conf;
reg [7:0] shift_regs;
reg sDATA_REQ;
reg sDATA_REQ_CONF;
reg sCS_REQ;
reg sCS_REQ_CONF;
reg [5:0]  LUT_INDEX;
reg sDATA_MOSI;
reg sDATA_MOSI_CONF;
wire [39:0] sDATA;
reg [39:0] LUT_DATA;
reg mSTART;
reg irq;
reg sCE_REQ;

integer delay_count;
integer shift_count;
integer shift_count_conf;

parameter LUT_SIZE = 7;

assign SS_N =  (LUT_INDEX < LUT_SIZE) ? sCS_REQ_CONF : sCS_REQ;
assign MOSI = (LUT_INDEX < LUT_SIZE) ? sDATA_MOSI_CONF : sDATA_MOSI;
assign CE = sCE_REQ;


always@(negedge RESET_N or posedge iCLK)
begin
	if(!RESET_N)
	  begin
	    mSTART	<=	0;
	  end
	else
	  begin
		if(DO_START)
		  mSTART	<=	1;
		if(DO_STOP)
		  mSTART	<=	0;		
	  end
end


always@(negedge RESET_N or posedge iCLK)
begin
  if (!RESET_N)
    begin
      delay_count = 0;
      sCE_REQ <= 1'b0;
    end
  else
    begin
      if (delay_count < 400)
	    begin
		  delay_count = delay_count+1;		
		  irq <= 1'b0;		
		  if ((delay_count > 20) && (delay_count < 220))
		  begin
	       sCE_REQ <= 1'b1;
	      end
	      else
	      begin
	        sCE_REQ <= 1'b0;
	      end    					    					    					    						    				
	    end
	  else 
	    begin
	      irq <= 1'b1;
	      delay_count = 0;
	      sCE_REQ <= 1'b0;
        end
    end
end

always @(negedge RESET_N or posedge iCLK)
begin
  if (!RESET_N)
    begin
      LUT_INDEX	<=	0;
    end
  else
    begin
      if ((LUT_INDEX < LUT_SIZE) && (irq == 1'b1))//
      begin
        LUT_INDEX <= LUT_INDEX+1;     
      end
    end
end


always @(negedge RESET_N or posedge iCLK)
begin
  if(!RESET_N)
  begin
	shift_count_conf = 0;
	sDATA_MOSI_CONF <= 1'b1;	
	shift_regs_conf <= 16'b0000000000000000;
	sDATA_REQ_CONF <= 1'b0;	
	sCS_REQ_CONF <= 1'b0;	 					  			
  end
  else 
  begin
	if (LUT_INDEX < LUT_SIZE)
	begin
	  if(shift_count_conf < 16)
	  begin
		sCS_REQ_CONF <= 1'b0;	          
        sDATA_MOSI_CONF <= shift_regs_conf[15];		                    
		shift_regs_conf[15:1] <= shift_regs_conf[14:0];			            
		shift_count_conf = shift_count_conf + 1;	
		sDATA_REQ_CONF <= 1'b0;		  			                           	                                    	
	  end
	  else
	  begin
	    sDATA_MOSI_CONF <= 1'b0;
	    sCS_REQ_CONF <= 1'b1;	  
	    if(irq  == 1'b1)
	    begin		  
		  sDATA_REQ_CONF <= 1'b1;
		  shift_count_conf = 0; 	
		  shift_regs_conf[15:0] <= LUT_DATA;				    
		end
	  end
	end
    else
	begin
      sDATA_MOSI_CONF <= 1'b0;
      sCS_REQ_CONF <= 1'b1;	
    end
  end
end

always @(negedge RESET_N or posedge iCLK)
begin
  if(!RESET_N)
  begin
	shift_count = 0;
	sDATA_MOSI <= 1'b1;	
	shift_regs <= 8'b00000000;
	sDATA_REQ = 1'b0;	
	sCS_REQ <= 1'b0;	 					  			
  end
  else 
  begin
	if (mSTART == 1'b1) 
	begin
	  if(shift_count < 8)
	  begin
		sCS_REQ <= 1'b0;	          
        sDATA_MOSI <= shift_regs[7];		                    
		shift_regs[7:1] <= shift_regs[6:0];			            
		shift_count = shift_count + 1;	
		sDATA_REQ <= 1'b0;		  			                           	                                    	
	  end
	  else
	  begin
	    sDATA_MOSI <= 1'b0;
	    sCS_REQ <= 1'b1;	  
	    if(irq  == 1'b1)
	    begin		  
		  sDATA_REQ <= 1'b1;
		  shift_count = 0; 	
		  shift_regs[7:0] <= 8'b10101010;//DATA;				    
		end
	  end
	end
    else
	begin
      sDATA_MOSI <= 1'b0;
      sCS_REQ <= 1'b1;	
    end
  end
end

always
begin
  case (LUT_INDEX)
    0:      LUT_DATA <= 16'b0010001100000011;      //  SPI_RW_Reg(WRITE_REG + SETUP_AW, (TX_AW-2));      
    1:      LUT_DATA <= 16'b0010011101110000;      //  SPI_RW_Reg(WRITE_REG + STATUS, 0x70);      
    2:      LUT_DATA <= 16'b0010000100000001;      //  SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); 
    3:      LUT_DATA <= 16'b0010001000000001;      //  SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);         
    4:      LUT_DATA <= 16'b0010100000001010;      //  SPI_RW_Reg(WRITE_REG + SETUP_RETR,0x0a);      
    5:      LUT_DATA <= 16'b1111110000000011; //16'b0010100100101000;      //  SPI_RW_Reg(WRITE_REG + RF_CH, 40);   
    6:      LUT_DATA <= 16'b0000001111111100; //16'b0010000000001110;      //  SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e);      
    default:
      LUT_DATA <= 16'b0000000000000000; 
      
  endcase
end

endmodule