de2_lcm_ccd.fit.rpt

在altera DE2 的开发板上采集图像

; Timing Models                      ; Final                                    ;
; Total logic elements               ; 1,438 / 33,216 ( 4 % )                   ;
;     Total combinational functions  ; 1,343 / 33,216 ( 4 % )                   ;
;     Dedicated logic registers      ; 885 / 33,216 ( 3 % )                     ;
; Total registers                    ; 897                                      ;
; Total pins                         ; 425 / 475 ( 89 % )                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 42,968 / 483,840 ( 9 % )                 ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 1 / 4 ( 25 % )                           ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Device I/O Standard                                                ; LVTTL                          ;                                ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                           ;
+-------------------------------------------+-----------------+------------------+--------------------------------+-----------+----------------+------------------------------------------------------------------------------+------------------+-----------------------+
; Node                                      ; Action          ; Operation        ; Reason                         ; Node Port ; Node Port Name ; Destination Node                                                             ; Destination Port ; Destination Port Name ;
+-------------------------------------------+-----------------+------------------+--------------------------------+-----------+----------------+------------------------------------------------------------------------------+------------------+-----------------------+
; I2C_AV_Config:u9|I2C_Controller:u0|SD[0]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[0]  ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[1]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[15] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[2]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[14] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[3]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[13] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[4]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[12] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[5]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[11] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[6]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[10] ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[7]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[9]  ; PORTADATAOUT     ;                       ;
; I2C_AV_Config:u9|I2C_Controller:u0|SD[8]  ; Packed Register ; Register Packing ; Timing optimization            ; REGOUT    ;                ; I2C_AV_Config:u9|altsyncram:Ram0_rtl_0|altsyncram_vov:auto_generated|q_a[8]  ; PORTADATAOUT     ;                       ;