test.hif

利用Verilog HDL对AD7705进行控制ADC采样

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1590
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
M10MHz
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
M10MHz.vhd
1207660612
4
# storage
db|test.(2).cnf
db|test.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
M10MHz:inst2
M10MHz:inst1
}
# end
# entity
test
# case_insensitive
# source_file
test.bdf
1207726278
23
# storage
db|test.(0).cnf
db|test.(0).cnf
# hierarchies {
|
}
# end
# entity
SetData
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SetData.vhd
1207728850
4
# storage
db|test.(1).cnf
db|test.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SetData:inst
}
# end
# complete