m10mhz.vhd

利用Verilog HDL对AD7705进行控制ADC采样

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------
entity M10MHz is
port
(
	 clk_ref:in std_logic;		
	 P10MHz:out std_logic
);
end M10MHz;

---------------------------------------------------
architecture M10MHz_body of M10MHz is

signal count:integer:=0;
signal divider:std_logic:='0';		

begin

process(clk_ref)
begin
	if(clk_ref'event and clk_ref='1')then
       count<=count+1;
       if count=4 then 
          P10MHz<='1';
       end if;
       if count=9 then 
          P10MHz<='0';
          count<=0;
       end if;
    	
	end if;		
end process;
end M10MHz_body ;