block1.map.rpt

此程序为Verilog控制ADC的全部程序

    Info: Duplicate register "ad_control:inst|half_n[19]" merged to single register "ad_control:inst|n[20]"
    Info: Duplicate register "ad_control:inst|half_n[18]" merged to single register "ad_control:inst|n[19]"
    Info: Duplicate register "ad_control:inst|half_n[17]" merged to single register "ad_control:inst|n[18]"
    Info: Duplicate register "ad_control:inst|half_n[16]" merged to single register "ad_control:inst|n[17]"
    Info: Duplicate register "ad_control:inst|half_n[15]" merged to single register "ad_control:inst|n[16]"
    Info: Duplicate register "ad_control:inst|half_n[14]" merged to single register "ad_control:inst|n[15]"
    Info: Duplicate register "ad_control:inst|half_n[13]" merged to single register "ad_control:inst|n[14]"
    Info: Duplicate register "ad_control:inst|half_n[12]" merged to single register "ad_control:inst|n[13]"
    Info: Duplicate register "ad_control:inst|half_n[11]" merged to single register "ad_control:inst|n[12]"
    Info: Duplicate register "ad_control:inst|half_n[10]" merged to single register "ad_control:inst|n[11]"
    Info: Duplicate register "ad_control:inst|half_n[9]" merged to single register "ad_control:inst|n[10]"
    Info: Duplicate register "ad_control:inst|half_n[8]" merged to single register "ad_control:inst|n[9]"
    Info: Duplicate register "ad_control:inst|half_n[7]" merged to single register "ad_control:inst|n[8]"
    Info: Duplicate register "ad_control:inst|half_n[6]" merged to single register "ad_control:inst|n[7]"
    Info: Duplicate register "ad_control:inst|half_n[5]" merged to single register "ad_control:inst|n[6]"
    Info: Duplicate register "ad_control:inst|half_n[4]" merged to single register "ad_control:inst|n[5]"
    Info: Duplicate register "ad_control:inst|half_n[3]" merged to single register "ad_control:inst|n[4]"
    Info: Duplicate register "ad_control:inst|half_n[2]" merged to single register "ad_control:inst|n[3]"
    Info: Duplicate register "ad_control:inst|half_n[1]" merged to single register "ad_control:inst|n[2]"
    Info: Duplicate register "ad_control:inst|half_n[0]" merged to single register "ad_control:inst|n[1]"
Warning: Reduced register "ad_control:inst|i[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|i[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|i[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|i[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|i[27]" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "ad_control:inst|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_g8m.tdf
    Info: Found entity 1: lpm_divide_g8m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9nh.tdf
    Info: Found entity 1: sign_div_unsign_9nh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_2ue.tdf
    Info: Found entity 1: alt_u_div_2ue
Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf
    Info: Found entity 1: add_sub_3dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf
    Info: Found entity 1: add_sub_4dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_kec.tdf
    Info: Found entity 1: add_sub_kec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lec.tdf
    Info: Found entity 1: add_sub_lec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mec.tdf
    Info: Found entity 1: add_sub_mec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_nec.tdf
    Info: Found entity 1: add_sub_nec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_oec.tdf
    Info: Found entity 1: add_sub_oec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_pec.tdf
    Info: Found entity 1: add_sub_pec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qec.tdf
    Info: Found entity 1: add_sub_qec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_rec.tdf
    Info: Found entity 1: add_sub_rec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_sec.tdf
    Info: Found entity 1: add_sub_sec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_tec.tdf
    Info: Found entity 1: add_sub_tec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf
    Info: Found entity 1: add_sub_5dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_uec.tdf
    Info: Found entity 1: add_sub_uec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_vec.tdf
    Info: Found entity 1: add_sub_vec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_0fc.tdf
    Info: Found entity 1: add_sub_0fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_1fc.tdf
    Info: Found entity 1: add_sub_1fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_2fc.tdf
    Info: Found entity 1: add_sub_2fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_3fc.tdf
    Info: Found entity 1: add_sub_3fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4fc.tdf
    Info: Found entity 1: add_sub_4fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5fc.tdf
    Info: Found entity 1: add_sub_5fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6fc.tdf
    Info: Found entity 1: add_sub_6fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_7fc.tdf
    Info: Found entity 1: add_sub_7fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf
    Info: Found entity 1: add_sub_6dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_8fc.tdf
    Info: Found entity 1: add_sub_8fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_9fc.tdf
    Info: Found entity 1: add_sub_9fc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf
    Info: Found entity 1: add_sub_7dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_8dc.tdf
    Info: Found entity 1: add_sub_8dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_9dc.tdf
    Info: Found entity 1: add_sub_9dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_adc.tdf
    Info: Found entity 1: add_sub_adc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_bdc.tdf
    Info: Found entity 1: add_sub_bdc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_jec.tdf
    Info: Found entity 1: add_sub_jec
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mac.tdf
    Info: Found entity 1: add_sub_mac
Info: Implemented 1290 device resources after synthesis - the final resource count might be different
    Info: Implemented 45 input pins
    Info: Implemented 13 output pins
    Info: Implemented 1232 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
    Info: Processing ended: Wed Jun 20 21:27:37 2007
    Info: Elapsed time: 00:00:12