block1.map.rpt

来自「此程序为Verilog控制ADC的全部程序」· RPT 代码 · 共 449 行 · 第 1/4 页

;                   |add_sub_8dc:add_sub_5|  ; 9 (9)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_8dc:add_sub_5  ;
;                   |add_sub_8fc:add_sub_30| ; 34 (34)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 34 (34)      ; 0 (0)             ; 0 (0)            ; 34 (34)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_8fc:add_sub_30 ;
;                   |add_sub_9dc:add_sub_6|  ; 7 (7)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 7 (7)           ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_9dc:add_sub_6  ;
;                   |add_sub_adc:add_sub_7|  ; 11 (11)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 11 (11)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_adc:add_sub_7  ;
;                   |add_sub_bdc:add_sub_8|  ; 9 (9)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_bdc:add_sub_8  ;
;                   |add_sub_jec:add_sub_9|  ; 10 (10)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_jec:add_sub_9  ;
;                   |add_sub_kec:add_sub_10| ; 14 (14)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; 14 (14)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_kec:add_sub_10 ;
;                   |add_sub_lec:add_sub_11| ; 12 (12)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 0 (0)            ; 12 (12)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_lec:add_sub_11 ;
;                   |add_sub_mec:add_sub_12| ; 13 (13)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 0 (0)            ; 13 (13)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_mec:add_sub_12 ;
;                   |add_sub_nec:add_sub_13| ; 14 (14)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; 14 (14)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_nec:add_sub_13 ;
;                   |add_sub_oec:add_sub_14| ; 18 (18)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_oec:add_sub_14 ;
;                   |add_sub_pec:add_sub_15| ; 19 (19)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 19 (19)      ; 0 (0)             ; 0 (0)            ; 19 (19)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_pec:add_sub_15 ;
;                   |add_sub_qec:add_sub_16| ; 20 (20)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 20 (20)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_qec:add_sub_16 ;
;                   |add_sub_rec:add_sub_17| ; 18 (18)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_rec:add_sub_17 ;
;                   |add_sub_sec:add_sub_18| ; 19 (19)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 19 (19)      ; 0 (0)             ; 0 (0)            ; 19 (19)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_sec:add_sub_18 ;
;                   |add_sub_tec:add_sub_19| ; 23 (23)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 23 (23)      ; 0 (0)             ; 0 (0)            ; 23 (23)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_tec:add_sub_19 ;
;                   |add_sub_uec:add_sub_20| ; 21 (21)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 21 (21)      ; 0 (0)             ; 0 (0)            ; 21 (21)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_uec:add_sub_20 ;
;                   |add_sub_vec:add_sub_21| ; 22 (22)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; 0 (0)      ; |block1|ad_control:inst|lpm_divide:Div0|lpm_divide_g8m:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_2ue:divider|add_sub_vec:add_sub_21 ;
+--------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; No         ; |block1|ad_control:inst|i~63 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ad_control:inst ;
+----------------+----------------------------+----------------+
; Parameter Name ; Value                      ; Type           ;
+----------------+----------------------------+----------------+
; system_clock   ; 10110111000110110000000000 ; Binary         ;
+----------------+----------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ad_control:inst|lpm_divide:Div0 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 26             ; Untyped                                ;
; LPM_WIDTHD             ; 32             ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_g8m ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Jun 20 21:27:26 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off block1 -c block1
Info: Found 1 design units, including 1 entities, in source file ad_control.v
    Info: Found entity 1: ad_control
Info: Found 1 design units, including 1 entities, in source file block1.bdf
    Info: Found entity 1: block1
Info: Elaborating entity "block1" for the top level hierarchy
Info: Elaborating entity "ad_control" for hierarchy "ad_control:inst"
Warning (10101): Verilog HDL unsupported feature warning at ad_control.v(38): Initial Construct is not supported and will be ignored
Warning: Reduced register "ad_control:inst|n[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|n[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|n[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|n[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|n[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|n[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "ad_control:inst|half_n[25]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "ad_control:inst|half_n[24]" merged to single register "ad_control:inst|n[25]"
    Info: Duplicate register "ad_control:inst|half_n[23]" merged to single register "ad_control:inst|n[24]"
    Info: Duplicate register "ad_control:inst|half_n[22]" merged to single register "ad_control:inst|n[23]"
    Info: Duplicate register "ad_control:inst|half_n[21]" merged to single register "ad_control:inst|n[22]"
    Info: Duplicate register "ad_control:inst|half_n[20]" merged to single register "ad_control:inst|n[21]"