wed.zsf

此程序为Verilog控制ADC的全部程序

E:/FPGA/project/ADControl/db/block1.sim.vwf	2658054	2696804	775	38750	0
E:/FPGA/project/ADControl/block1.vwf	0	1000000	20	1000	0
block1.vwf	0	100000000	20	1000	0