prev_cmp_led.tan.qmsg

是vhdl语言

{ "Info" "ITDB_TSU_RESULT" "count:inst\|count_4\[1\] en clk 1.807 ns register " "Info: tsu for register \"count:inst\|count_4\[1\]\" (data pin = \"en\", clock pin = \"clk\") is 1.807 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.264 ns + Longest pin register " "Info: + Longest pin to register delay is 8.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns en 1 PIN PIN_AE6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_AE6; Fanout = 5; PIN Node = 'en'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 440 0 168 456 "en" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.744 ns) + CELL(0.660 ns) 8.264 ns count:inst\|count_4\[1\] 2 REG LCFF_X40_Y23_N7 14 " "Info: 2: + IC(6.744 ns) + CELL(0.660 ns) = 8.264 ns; Loc. = LCFF_X40_Y23_N7; Fanout = 14; REG Node = 'count:inst\|count_4\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.404 ns" { en count:inst|count_4[1] } "NODE_NAME" } } { "count.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/count.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 18.39 % ) " "Info: Total cell delay = 1.520 ns ( 18.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.744 ns ( 81.61 % ) " "Info: Total interconnect delay = 6.744 ns ( 81.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.264 ns" { en count:inst|count_4[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.264 ns" { en {} en~combout {} count:inst|count_4[1] {} } { 0.000ns 0.000ns 6.744ns } { 0.000ns 0.860ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "count.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/count.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.421 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.421 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P25 8 " "Info: 1: + IC(0.000 ns) +