prev_cmp_led.tan.qmsg

是vhdl语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 128.8 MHz 7.764 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 128.8 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 7.764 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.669 ns + Longest register register " "Info: + Longest register to register delay is 3.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 1 REG LCFF_X35_Y24_N7 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y24_N7; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.398 ns) 0.724 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LCCOMB_X35_Y24_N14 6 " "Info: 2: + IC(0.326 ns) + CELL(0.398 ns) = 0.724 ns; Loc. = LCCOMB_X35_Y24_N14; Fanout = 6; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.724 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.150 ns) 1.284 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 3 COMB LCCOMB_X36_Y24_N26 4 " "Info: 3: + IC(0.410 ns) + CELL(0.150 ns) = 1.284 ns; Loc. = LCCOMB_X36_Y24_N26; Fanout = 4; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 801 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.150 ns) 1.705 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55 4 COMB LCCOMB_X36_Y24_N10 18 " "Info: 4: + IC(0.271 ns) + CELL(0.150 ns) = 1.705 ns; Loc. = LCCOMB_X36_Y24_N10; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.421 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 829 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.150 ns) 2.108 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 5 COMB LCCOMB_X36_Y24_N2 1 " "Info: 5: + IC(0.253 ns) + CELL(0.150 ns) = 2.108 ns; Loc. = LCCOMB_X36_Y24_N2; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.403 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 514 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.420 ns) 2.777 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 6 COMB LCCOMB_X36_Y24_N12 1 " "Info: 6: + IC(0.249 ns) + CELL(0.420 ns) = 2.777 ns; Loc. = LCCOMB_X36_Y24_N12; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.669 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 514 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 3.174 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LCCOMB_X36_Y24_N30 1 " "Info: 7: + IC(0.247 ns) + CELL(0.150 ns) = 3.174 ns; Loc. = LCCOMB_X36_Y24_N30; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.397 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.150 ns) 3.585 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LCCOMB_X36_Y24_N16 1 " "Info: 8: + IC(0.261 ns) + CELL(0.150 ns) = 3.585 ns; Loc. = LCCOMB_X36_Y24_N16; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.411 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.669 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LCFF_X36_Y24_N17 2 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 3.669 ns; Loc. = LCFF_X36_Y24_N17; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.652 ns ( 45.03 % ) " "Info: Total cell delay = 1.652 ns ( 45.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.017 ns ( 54.97 % ) " "Info: Total interconnect delay = 2.017 ns ( 54.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.669 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.669 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.326ns 0.410ns 0.271ns 0.253ns 0.249ns 0.247ns 0.261ns 0.000ns } { 0.000ns 0.398ns 0.150ns 0.150ns 0.150ns 0.420ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.428 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 257 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G0; Fanout = 257; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.537 ns) 4.428 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X36_Y24_N17 2 " "Info: 3: + IC(1.003 ns) + CELL(0.537 ns) = 4.428 ns; Loc. = LCFF_X36_Y24_N17; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.13 % ) " "Info: Total cell delay = 0.537 ns ( 12.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.891 ns ( 87.87 % ) " "Info: Total interconnect delay = 3.891 ns ( 87.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.428 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.428 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.003ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.427 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 257 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G0; Fanout = 257; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 4.427 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 3 REG LCFF_X35_Y24_N7 12 " "Info: 3: + IC(1.002 ns) + CELL(0.537 ns) = 4.427 ns; Loc. = LCFF_X35_Y24_N7; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.13 % ) " "Info: Total cell delay = 0.537 ns ( 12.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.890 ns ( 87.87 % ) " "Info: Total interconnect delay = 3.890 ns ( 87.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.427 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.427 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 2.888ns 1.002ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.428 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.428 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.003ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.427 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.427 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 2.888ns 1.002ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.669 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.669 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.326ns 0.410ns 0.271ns 0.253ns 0.249ns 0.247ns 0.261ns 0.000ns } { 0.000ns 0.398ns 0.150ns 0.150ns 0.150ns 0.420ns 0.150ns 0.150ns 0.084ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.428 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.428 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.888ns 1.003ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.427 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.427 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 2.888ns 1.002ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "auto_stp_external_clock_0 register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\] register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 261.23 MHz 3.828 ns Internal " "Info: Clock \"auto_stp_external_clock_0\" has Internal fmax of 261.23 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig\" (period= 3.828 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.611 ns + Longest register register " "Info: + Longest register to register delay is 3.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\] 1 REG LCFF_X55_Y24_N17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X55_Y24_N17; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.438 ns) 0.790 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~92 2 COMB LCCOMB_X55_Y24_N10 1 " "Info: 2: + IC(0.352 ns) + CELL(0.438 ns) = 0.790 ns; Loc. = LCCOMB_X55_Y24_N10; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~92'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.790 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.410 ns) 1.648 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94 3 COMB LCCOMB_X56_Y24_N28 21 " "Info: 3: + IC(0.448 ns) + CELL(0.410 ns) = 1.648 ns; Loc. = LCCOMB_X56_Y24_N28; Fanout = 21; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.858 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.419 ns) 2.352 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address~11 4 COMB LCCOMB_X56_Y24_N16 2 " "Info: 4: + IC(0.285 ns) + CELL(0.419 ns) = 2.352 ns; Loc. = LCCOMB_X56_Y24_N16; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address~11'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.704 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.438 ns) 3.527 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig~28 5 COMB LCCOMB_X53_Y24_N12 1 " "Info: 5: + IC(0.737 ns) + CELL(0.438 ns) = 3.527 ns; Loc. = LCCOMB_X53_Y24_N12; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig~28'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.175 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.611 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 6 REG LCFF_X53_Y24_N13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.611 ns; Loc. = LCFF_X53_Y24_N13; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.789 ns ( 49.54 % ) " "Info: Total cell delay = 1.789 ns ( 49.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.822 ns ( 50.46 % ) " "Info: Total interconnect delay = 1.822 ns ( 50.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.611 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.611 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.352ns 0.448ns 0.285ns 0.737ns 0.000ns } { 0.000ns 0.438ns 0.410ns 0.419ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "auto_stp_external_clock_0 destination 2.646 ns + Shortest register " "Info: + Shortest clock path from clock \"auto_stp_external_clock_0\" to destination register is 2.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns auto_stp_external_clock_0 1 CLK PIN_P26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P26; Fanout = 1; CLK Node = 'auto_stp_external_clock_0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns auto_stp_external_clock_0~clkctrl 2 COMB CLKCTRL_G7 236 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G7; Fanout = 236; COMB Node = 'auto_stp_external_clock_0~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.537 ns) 2.646 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 3 REG LCFF_X53_Y24_N13 2 " "Info: 3: + IC(0.997 ns) + CELL(0.537 ns) = 2.646 ns; Loc. = LCFF_X53_Y24_N13; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.05 % ) " "Info: Total cell delay = 1.536 ns ( 58.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.110 ns ( 41.95 % ) " "Info: Total interconnect delay = 1.110 ns ( 41.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.646 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.646 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.113ns 0.997ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "auto_stp_external_clock_0 source 2.649 ns - Longest register " "Info: - Longest clock path from clock \"auto_stp_external_clock_0\" to source register is 2.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns auto_stp_external_clock_0 1 CLK PIN_P26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P26; Fanout = 1; CLK Node = 'auto_stp_external_clock_0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns auto_stp_external_clock_0~clkctrl 2 COMB CLKCTRL_G7 236 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G7; Fanout = 236; COMB Node = 'auto_stp_external_clock_0~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.649 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\] 3 REG LCFF_X55_Y24_N17 4 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.649 ns; Loc. = LCFF_X55_Y24_N17; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.98 % ) " "Info: Total cell delay = 1.536 ns ( 57.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.113 ns ( 42.02 % ) " "Info: Total interconnect delay = 1.113 ns ( 42.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.649 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.649 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] {} } { 0.000ns 0.000ns 0.113ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.646 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.646 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.113ns 0.997ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.649 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.649 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] {} } { 0.000ns 0.000ns 0.113ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.611 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.611 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~92 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig~28 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.352ns 0.448ns 0.285ns 0.737ns 0.000ns } { 0.000ns 0.438ns 0.410ns 0.419ns 0.438ns 0.084ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.646 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.646 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.113ns 0.997ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.649 ns" { auto_stp_external_clock_0 auto_stp_external_clock_0~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.649 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~combout {} auto_stp_external_clock_0~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4] {} } { 0.000ns 0.000ns 0.113ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}