prev_cmp_led.tan.qmsg

是vhdl语言

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:inst2\|clkout " "Info: Detected ripple clock \"div:inst2\|clkout\" as buffer" {  } { { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 10 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "div:inst2\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div:inst2\|count\[15\] register div:inst2\|count\[24\] 246.79 MHz 4.052 ns Internal " "Info: Clock \"clk\" has Internal fmax of 246.79 MHz between source register \"div:inst2\|count\[15\]\" and destination register \"div:inst2\|count\[24\]\" (period= 4.052 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.835 ns + Longest register register " "Info: + Longest register to register delay is 3.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst2\|count\[15\] 1 REG LCFF_X61_Y15_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y15_N3; Fanout = 3; REG Node = 'div:inst2\|count\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { div:inst2|count[15] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.393 ns) 1.180 ns div:inst2\|Equal0~313 2 COMB LCCOMB_X62_Y16_N12 1 " "Info: 2: + IC(0.787 ns) + CELL(0.393 ns) = 1.180 ns; Loc. = LCCOMB_X62_Y16_N12; Fanout = 1; COMB Node = 'div:inst2\|Equal0~313'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { div:inst2|count[15] div:inst2|Equal0~313 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.413 ns) 1.861 ns div:inst2\|Equal0~315 3 COMB LCCOMB_X62_Y16_N0 1 " "Info: 3: + IC(0.268 ns) + CELL(0.413 ns) = 1.861 ns; Loc. = LCCOMB_X62_Y16_N0; Fanout = 1; COMB Node = 'div:inst2\|Equal0~315'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.681 ns" { div:inst2|Equal0~313 div:inst2|Equal0~315 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.393 ns) 2.503 ns div:inst2\|Equal0~320 4 COMB LCCOMB_X62_Y16_N10 14 " "Info: 4: + IC(0.249 ns) + CELL(0.393 ns) = 2.503 ns; Loc. = LCCOMB_X62_Y16_N10; Fanout = 14; COMB Node = 'div:inst2\|Equal0~320'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.642 ns" { div:inst2|Equal0~315 div:inst2|Equal0~320 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.275 ns) 3.751 ns div:inst2\|count~274 5 COMB LCCOMB_X62_Y14_N30 1 " "Info: 5: + IC(0.973 ns) + CELL(0.275 ns) = 3.751 ns; Loc. = LCCOMB_X62_Y14_N30; Fanout = 1; COMB Node = 'div:inst2\|count~274'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.248 ns" { div:inst2|Equal0~320 div:inst2|count~274 } "NODE_NAME" } } { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.835 ns div:inst2\|count\[24\] 6 REG LCFF_X62_Y14_N31 4 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.835 ns; Loc. = LCFF_X62_Y14_N31; Fanout = 4; REG Node = 'div:inst2\|count\[24\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { div:inst2|count~274 div:inst2|count[24] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.558 ns ( 40.63 % ) " "Info: Total cell delay = 1.558 ns ( 40.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.277 ns ( 59.37 % ) " "Info: Total interconnect delay = 2.277 ns ( 59.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.835 ns" { div:inst2|count[15] div:inst2|Equal0~313 div:inst2|Equal0~315 div:inst2|Equal0~320 div:inst2|count~274 div:inst2|count[24] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.835 ns" { div:inst2|count[15] {} div:inst2|Equal0~313 {} div:inst2|Equal0~315 {} div:inst2|Equal0~320 {} div:inst2|count~274 {} div:inst2|count[24] {} } { 0.000ns 0.787ns 0.268ns 0.249ns 0.973ns 0.000ns } { 0.000ns 0.393ns 0.413ns 0.393ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.680 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P25 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 288 -64 104 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns clk~clkctrl 2 COMB CLKCTRL_G4 33 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 288 -64 104 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.680 ns div:inst2\|count\[24\] 3 REG LCFF_X62_Y14_N31 4 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X62_Y14_N31; Fanout = 4; REG Node = 'div:inst2\|count\[24\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl div:inst2|count[24] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.31 % ) " "Info: Total cell delay = 1.536 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.144 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clk clk~clkctrl div:inst2|count[24] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[24] {} } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.683 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P25 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 288 -64 104 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns clk~clkctrl 2 COMB CLKCTRL_G4 33 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } } { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 288 -64 104 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 2.683 ns div:inst2\|count\[15\] 3 REG LCFF_X61_Y15_N3 3 " "Info: 3: + IC(1.034 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X61_Y15_N3; Fanout = 3; REG Node = 'div:inst2\|count\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { clk~clkctrl div:inst2|count[15] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl div:inst2|count[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[15] {} } { 0.000ns 0.000ns 0.113ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clk clk~clkctrl div:inst2|count[24] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[24] {} } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl div:inst2|count[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[15] {} } { 0.000ns 0.000ns 0.113ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.835 ns" { div:inst2|count[15] div:inst2|Equal0~313 div:inst2|Equal0~315 div:inst2|Equal0~320 div:inst2|count~274 div:inst2|count[24] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.835 ns" { div:inst2|count[15] {} div:inst2|Equal0~313 {} div:inst2|Equal0~315 {} div:inst2|Equal0~320 {} div:inst2|count~274 {} div:inst2|count[24] {} } { 0.000ns 0.787ns 0.268ns 0.249ns 0.973ns 0.000ns } { 0.000ns 0.393ns 0.413ns 0.393ns 0.275ns 0.084ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clk clk~clkctrl div:inst2|count[24] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[24] {} } { 0.000ns 0.000ns 0.113ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl div:inst2|count[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst2|count[15] {} } { 0.000ns 0.000ns 0.113ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}