deccount.vhd

是vhdl语言

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY deccount IS

	PORT(
		INCLK	:	IN	STD_LOGIC;						--	输入时钟源
		PRESET	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);	--	预制分频 N
		OUTCLK	:	BUFFER	STD_LOGIC					--  输出时钟
		);

END ENTITY;



ARCHITECTURE behavioural OF deccount IS

 SIGNAL		clk_G_CounterClk:	STD_LOGIC;
 SIGNAL		reg_G_divide	:	STD_LOGIC;
 SIGNAL		reg_G_Counter	:	STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

	clk_G_CounterClk <= INCLK XOR reg_G_divide;		-- 
	
	
	PROCESS(clk_G_CounterClk)
	BEGIN
	
		IF(clk_G_CounterClk'EVENT AND clk_G_CounterClk = '1') THEN
			
			IF(reg_G_Counter = "0000") THEN
			
				reg_G_Counter <= PRESET - 1;		-- 置整数分频值 N
				
				OUTCLK <= '1';
			ELSE
			
				reg_G_Counter <= reg_G_Counter - 1;	-- 模 N 计数器减法计数
				
				OUTCLK <= '0';
			END IF;
		
		END IF;
		
	END PROCESS;
	
	
	PROCESS(OUTCLK)
	BEGIN
		
		IF(OUTCLK'EVENT AND OUTCLK = '1') THEN
			
			reg_G_divide <= NOT reg_G_divide;	-- 输出时钟二分频
			
		END IF;
		
	END PROCESS;
	
END behavioural;