stp1.stp

是vhdl语言

<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C35 (0x020B40DD)" sof_file="" top_level_entity="led">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <multi attribute="window position" size="9" value="1032,697,398,124,0,50,124,0,0"/>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
  </global_info>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="0"/>
      <single attribute="data vertical scroll position" value="1"/>
      <single attribute="data horizontal scroll position" value="0"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom offset numerator" value="130944"/>
      <single attribute="zoom offset denominator" value="1"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2008/07/01 11:33:37  #0">
      <clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="clk" tap_mode="classic" type="input pin"/>
          <wire name="count:inst|q[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="div:inst2|clkin" tap_mode="classic" type="combinatorial"/>
          <wire name="div:inst2|clkout" tap_mode="classic" type="combinatorial"/>
          <wire name="full" tap_mode="classic" type="output pin"/>
          <wire name="trans:inst1|qout[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[7]" tap_mode="classic" type="combinatorial"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="clk" tap_mode="classic" type="input pin"/>
          <wire name="count:inst|q[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="count:inst|q[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="div:inst2|clkin" tap_mode="classic" type="combinatorial"/>
          <wire name="div:inst2|clkout" tap_mode="classic" type="combinatorial"/>
          <wire name="full" tap_mode="classic" type="output pin"/>
          <wire name="trans:inst1|qout[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="trans:inst1|qout[7]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="clk"/>
          <net is_signal_inverted="no" name="full"/>
          <net is_signal_inverted="no" name="div:inst2|clkin"/>
          <net is_signal_inverted="no" name="div:inst2|clkout"/>
          <bus is_signal_inverted="no" link="all" name="trans:inst1|qout" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="trans:inst1|qout[0]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[1]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[2]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[3]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[4]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[5]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[6]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[7]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="count:inst|q" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="count:inst|q[0]"/>
            <net is_signal_inverted="no" name="count:inst|q[1]"/>
            <net is_signal_inverted="no" name="count:inst|q[2]"/>
            <net is_signal_inverted="no" name="count:inst|q[3]"/>
          </bus>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="clk"/>
          <net is_signal_inverted="no" name="full"/>
          <net is_signal_inverted="no" name="div:inst2|clkin"/>
          <net is_signal_inverted="no" name="div:inst2|clkout"/>
          <bus is_signal_inverted="no" link="all" name="trans:inst1|qout" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="trans:inst1|qout[0]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[1]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[2]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[3]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[4]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[5]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[6]"/>
            <net is_signal_inverted="no" name="trans:inst1|qout[7]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="count:inst|q" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="count:inst|q[0]"/>
            <net is_signal_inverted="no" name="count:inst|q[1]"/>
            <net is_signal_inverted="no" name="count:inst|q[2]"/>
            <net is_signal_inverted="no" name="count:inst|q[3]"/>
          </bus>
        </setup_view>
      </presentation>
      <trigger global_temp="1" name="trigger: 2008/07/01 11:33:37  #1" position="pre" power_up_trigger_mode="false" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">'trans:inst1|qout[0]' == rising edge &amp;&amp; 'trans:inst1|qout[1]' == rising edge &amp;&amp; 'trans:inst1|qout[2]' == rising edge &amp;&amp; 'trans:inst1|qout[3]' == rising edge &amp;&amp; 'trans:inst1|qout[4]' == rising edge &amp;&amp; 'trans:inst1|qout[5]' == rising edge &amp;&amp; 'trans:inst1|qout[6]' == rising edge &amp;&amp; 'trans:inst1|qout[7]' == rising edge
            <power_up enabled="yes">
            </power_up>
            <op_node>
              <op_node left="645" top="119" type="Advanced Trigger Level Result"/>
            </op_node>
          </level>
        </events>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
</session>