div.tan.rpt

是vhdl语言

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[5]  ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 1.581 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[8]  ; count[11] ; clkin      ; clkin    ; None                        ; None                      ; 1.532 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[6]  ; count[11] ; clkin      ; clkin    ; None                        ; None                      ; 1.518 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[7]  ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 1.522 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]  ; count[6]  ; clkin      ; clkin    ; None                        ; None                      ; 1.506 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[9]  ; count[11] ; clkin      ; clkin    ; None                        ; None                      ; 1.486 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[0]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 1.480 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[8]  ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 1.461 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[3]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 1.458 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 1.450 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[6]  ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 1.447 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[9]  ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 1.415 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[0]  ; count[4]  ; clkin      ; clkin    ; None                        ; None                      ; 1.409 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[4]  ; count[6]  ; clkin      ; clkin    ; None                        ; None                      ; 1.396 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[3]  ; count[4]  ; clkin      ; clkin    ; None                        ; None                      ; 1.387 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]  ; count[4]  ; clkin      ; clkin    ; None                        ; None                      ; 1.379 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[5]  ; count[6]  ; clkin      ; clkin    ; None                        ; None                      ; 1.297 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]  ; count[4]  ; clkin      ; clkin    ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[0]  ; count[2]  ; clkin      ; clkin    ; None                        ; None                      ; 1.267 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[4]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 1.237 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[10] ; count[11] ; clkin      ; clkin    ; None                        ; None                      ; 1.237 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]  ; count[2]  ; clkin      ; clkin    ; None                        ; None                      ; 1.237 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[0]  ; count[1]  ; clkin      ; clkin    ; None                        ; None                      ; 1.196 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[4]  ; count[4]  ; clkin      ; clkin    ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[10] ; count[10] ; clkin      ; clkin    ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]  ; count[1]  ; clkin      ; clkin    ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[6]  ; count[6]  ; clkin      ; clkin    ; None                        ; None                      ; 0.848 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[5]  ; count[5]  ; clkin      ; clkin    ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]  ; count[2]  ; clkin      ; clkin    ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[11] ; count[11] ; clkin      ; clkin    ; None                        ; None                      ; 0.817 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; full      ; full      ; clkin      ; clkin    ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 6.061 ns   ; full ; clkout ; clkin      ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Thu Jun 26 17:02:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" has Internal fmax of 335.8 MHz between source register "count[6]" and destination register "full" (period= 2.978 ns)
    Info: + Longest register to register delay is 2.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y7_N17; Fanout = 3; REG Node = 'count[6]'
        Info: 2: + IC(0.512 ns) + CELL(0.398 ns) = 0.910 ns; Loc. = LCCOMB_X1_Y7_N20; Fanout = 1; COMB Node = 'Equal0~120'
        Info: 3: + IC(0.445 ns) + CELL(0.410 ns) = 1.765 ns; Loc. = LCCOMB_X2_Y7_N0; Fanout = 7; COMB Node = 'Equal0~122'
        Info: 4: + IC(0.491 ns) + CELL(0.420 ns) = 2.676 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 1; COMB Node = 'full~43'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.760 ns; Loc. = LCFF_X1_Y7_N13; Fanout = 2; REG Node = 'full'
        Info: Total cell delay = 1.312 ns ( 47.54 % )
        Info: Total interconnect delay = 1.448 ns ( 52.46 % )
    Info: - Smallest clock skew is -0.004 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 2.665 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clkin~clkctrl'
            Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X1_Y7_N13; Fanout = 2; REG Node = 'full'
            Info: Total cell delay = 1.536 ns ( 57.64 % )
            Info: Total interconnect delay = 1.129 ns ( 42.36 % )
        Info: - Longest clock path from clock "clkin" to source register is 2.669 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clkin~clkctrl'
            Info: 3: + IC(1.015 ns) + CELL(0.537 ns) = 2.669 ns; Loc. = LCFF_X2_Y7_N17; Fanout = 3; REG Node = 'count[6]'
            Info: Total cell delay = 1.536 ns ( 57.55 % )
            Info: Total interconnect delay = 1.133 ns ( 42.45 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clkin" to destination pin "clkout" through register "full" is 6.061 ns
    Info: + Longest clock path from clock "clkin" to source register is 2.665 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clkin~clkctrl'
        Info: 3: + IC(1.011 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X1_Y7_N13; Fanout = 2; REG Node = 'full'
        Info: Total cell delay = 1.536 ns ( 57.64 % )
        Info: Total interconnect delay = 1.129 ns ( 42.36 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.146 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y7_N13; Fanout = 2; REG Node = 'full'
        Info: 2: + IC(0.514 ns) + CELL(2.632 ns) = 3.146 ns; Loc. = PIN_Y4; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.632 ns ( 83.66 % )
        Info: Total interconnect delay = 0.514 ns ( 16.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Thu Jun 26 17:02:54 2008
    Info: Elapsed time: 00:00:03